T25S16AFEPR datasheet(18/74 Pages) HMSEMI

18 / 74 page

Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 4 of 5)

SFDP

Parameter

Relative Byte

Address

SFDP

Dword

Name

Data

Description

60h

JEDEC

Basic

Flash

Parameter

Dword-13

7Ah

Bits 31:24 = Erase Suspend Instruction = 75h

Bits 23:16 = Erase Resume Instruction = 7Ah

Bits 15:8 = Program Suspend Instruction = 75h

Bits 7:0 = Program Resume Instruction = 7Ah

61h

75h

62h

7Ah

63h

75h

64h

JEDEC

Basic

Flash

Parameter

Dword-14

F7h

Bit 31 = Deep Power-Down Supported = 0

Bits 30:23 = Enter Deep Power-Down Instruction = B9h

Bits 22:15 = Exit Deep Power-Down Instruction = ABh

Bits 14:13 = Exit Deep Power-Down to next operation delay units = (00b: 128 ns,

01b: 1 μs,

10b: 8 μs, 11b: 64 μs) = 1 μs = 01b

Bits 12:8 = Exit Deep Power-Down to next operation delay count = 00010b, Exit

Deep Power-Down to next operation delay = (count+1)*units = 3*1 μs=3 μs

Bits 7:4 = RFU = 1111b

Bit 3:2 = Status Register Polling Device Busy

= 01b: Legacy status polling supported = Use legacy polling by reading the Status

Bits 1:0 = RFU = 11b

Binary Fields: 0-10111001-10101011-01-00010-1111-01-11

Nibble Format: 0101_1100_1101_0101_1010_0010_1111_0111

Hex Format: 5C_D5_A2_F7

65h

A2h

66h

D5h

67h

5Ch

68h

JEDEC

Basic

Flash

Parameter

Dword-15

19h

Bits 31:24 = RFU = FFh

Bit 23 = Hold and WP Disable = set QE(bit 1 of SR2) high = 1b

Bits 22:20 = Quad Enable Requirements

= 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read

Status instruction 05h. Status register 2 is read using instruction 35h. QE is set via

Write Status instruction 01h with two data bytes where bit 1 of the second byte is

one. It is cleared via Write Status with two data bytes where bit 1 of the second byte

is zero.

Bits 19:16 0-4-4 Mode Entry Method

= xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode

+ x1xxb: Mode Bits[7:0] = Axh

+ 1xxxb: RFU

= 1101b

Bits 15:10 0-4-4 Mode Exit Method

= xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current

read operation

+ xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate

the mode prior to the next read operation.

+ 11_x1xx: RFU

= 111101b

Bit 9 = 0-4-4 mode supported = 1

Bits 8:4 = 4-4-4 mode enable sequences = 0_0001b: set QE per QER description

above, then issue instruction 38h

Bits 3:0 = 4-4-4 mode disable sequences

= xxx1b: issue FFh instruction

+ 1xxxb: issue the Soft Reset 66/99 sequence

= 1001b

Binary Fields: 11111111-1-101-1101-111101-1-00001-1001

Nibble Format: 1111_1111-1101-1101-1111_0110_0001-1001

Hex Format: FF_DD_F6_19

69h

F6h

6Ah

DDh

6Bh

FFh

HM25Q128A

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