T25S16AFEPR datasheet(25/74 Pages) HMSEMI

25 / 74 page

6.2.5 Sector / Block Protect (SEC)

The non-volatile Sector / Block Protect bit (SEC SR1[6]) controls if the Block Protect Bits (BP2, BP1, BP0)

protect either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) of the array as shown in Section 6.4.2, Block

Protection Maps. The default setting is SEC=0.

6.2.6 Complement Protect (CMP)

The Complement Protect bit (CMP SR2[6]) is a non-volatile read / write bit in the Status Register (SR2[6]).

It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array

protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be

reversed. For instance, when CMP=0, a top 4-kB sector can be protected while the rest of the array is not;

when CMP=1, the top 4-kB sector will become unprotected while the rest of the array become read-only.

Refer to Section 6.3.2, Block Protection Maps for details. The default setting is CMP=0.

6.2.7 The Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read / write bits in the Status Register

(SR2[0] and SR1[7]). The SRP bits control the method of write protection: software protection, hardware

protection, power supply lock-down, or one time programmable (OTP) protection.

Table 6.4 Status Register Protect

SRP1

SRP0

WP#

Status Register

Description

Software Protection

WP# pin has no control. SR1 ,SR2 and SR3 can be written to

after a Write Enable command, WEL=1. [Factory Default]

Hardware Protected

When WP# pin is low the SR1, SR2 and SR3 are locked and

cannot be written.

Hardware

Unprotected

When WP# pin is high SR1 ,SR2 and SR3 are unlocked and

can be written to after a Write Enable command, WEL=1.

Power Supply Lock

Down

SR1 ,SR2 and SR3 are protected and cannot be written to again

until the next power-down, power-up cycle. (1)

One Time Program (2)

SR1 ,SR2 and SR3 are permanently protected and cannot be

written.

Notes:

1. When SRP1, SRP0 = (1, 0), a power-down, power-up, or Software Reset cycle will change SRP1, SRP0 to (0, 0) state.

2. The One-Time Program feature is available upon special order. Contact Zbit for details.

3. Busy, WEL, and SUS (SR1[1:0] and SR2[7]) are volatile read only status bits that are never affected by the Write Status

Registers command.

4. The non-volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits and the OTP

LB3-LB1 bits are not writable when protected by the SRP bits and WP# as shown in the table. The non-volatile version of

these Status Register bits is selected for writing when the Write Enable (06h) command precedes the Write Status Registers

(01h) command.

5. The volatile version of HRSW, DRV1, DRV0, HFQ, WPS, CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR3[7:4,2],

SR2[6,1,0] and SR1[6:2]) bits are not writable when protected by the SRP bits and WP# as shown in the table. The volatile

version of these Status Register bits is selected for writing when the Write Enable for volatile Status Register (50h)

command precedes the Write Status Registers (01h) command. There is no volatile version of the LB3-LB1 bits and these

bits are not affected by a volatile Write Status Registers command.

6.2.8 Erase / Program Suspend Status (SUS)

The Suspend Status bit is a read only bit in the status register (SR2[7]) that is set to 1 after executing an

Erase / Program Suspend (75h) command. The SUS status bit is cleared to 0 by Erase / Program Resume

(7Ah) command as well as a power-down, power-up cycle.

6.2.9 Security Register Lock Bits (LB3, LB2, LB1)

The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status

state of LB[3:1] is 0, Security Registers 1 to 3 are unlocked. LB[3:1] can be set to 1 individually using the Write

HM25Q128A

T25S16AFEPR Scheda tecnica(PDF) 25 Page - Shenzhen Huazhimei Semiconductor Co., Ltd

T25S16AFEPR Scheda tecnica(HTML) 25 Page - Shenzhen Huazhimei Semiconductor Co., Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Scheda tecnica Scarica

Link URL