T25S16AFEPR datasheet(69/74 Pages) HMSEMI

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8.5. AC Electrical Characteristics

Table 8.6 AC Electrical Characteristics

SYMBOL

ALT

Parameter

SPEC

UNIT

MIN

TYP

MAX

Clock frequency for all QPI/Quad IO instructions with

HFQ, Vcc=2.7V-3.6V

D.C.

104

MHz

Clock frequency for all SPI instructions (except 03h/EBh)

Vcc=2.7V-3.6V

D.C.

104

MHz

Clock frequency for all SPI instructions (except 03h/EBh)

Vcc=2.3V-2.7V(1)

D.C.

MHz

Clock frequency for Read Data instruction (03h)

D.C.

MHz

tCLH, tCLL(2)

Clock High, Low Time for all instructions except Read

Data (03h)

tCRLH, tCRLL(2)

Clock High, Low Time for Read Data (03h) instruction

tCLCH(3)

Clock Rise Time peak to peak

0.1

V/ns

tCHCL(3)

Clock Fall Time peak to peak

0.1

V/ns

tSLCH

tCSS

CS# Active Setup Time relative to CLK

tCHSL

CS# Not Active Hold Time relative to CLK

tDVCH

tDSU

Data In Setup Time

tCHDX

tDH

Data In Hold Time

tCHSH

CS# Active Hold Time relative to CLK

tSHCH

CS# Not Active Setup Time relative to CLK

tSHSL1

tCSH1

CS# Deselect Time SPI (Array ReadArray Read)

tSHSL2

tCSH2

CS# Deselect Time for Erase/ProgramRead SR

Volatile Status Register Write Time

tSHSL3

tCSH3

CS# Deselect Time for non Array Read→Array

Read(Dual IO, Quad IO and QPI Read)

100

tSHQZ(3)

tDIS

Output Disable Time

tCLQV

Clock Low to Output Valid 2.7V- 3.6V

tCLQV

Clock Low to Output Valid 2.3V- 2.7V

tCLQX

tHO

Output Hold Time

tHLCH

HOLD# Active Setup Time relative to CLK

tCHHH

HOLD# Active Hold Time relative to CLK

tHHCH

HOLD# Not Active Setup Time relative to CLK

tCHHL

HOLD# Not Active Hold Time relative to CLK

tHHQX

tLZ(3)

HOLD# to Output Low-Z

tHLQZ

tHZ(3)

HOLD# to Output High-Z

tWHSL(4)

Write Protect Setup Time Before CS# Low

tSHWL(4)

Write Protect Hold Time After CS# High

100

tDP(3)

CS# High to Power-down Mode

μs

tRES1(3)

CS# High to Standby Mode without Electronic Signature

Read

μs

tRES2(3)

CS# High to Standby Mode with Electronic Signature

Read

μs

tsus(3)

CS# High to next Command after Suspend

μs

Write Status Register Time

100

tPP

Page Program Time

0.5

1.5

tSE

Sector Erase Time (4KB)

200

tBE1

Block Erase Time (32KB)

0.15

0.8

tBE2

Block Erase Time (64KB)

0.25

tCE

Chip Erase Time

200

tRCH(3)

End of Reset Instruction to CE# High

tRST(3)(5)

CE# High to next Instruction after Reset

μs

Notes:

(1)With HFQ, the clock frequency of all SPI instructions(except 03h/EBh) can reach 104MHz.

(2)Clock high + Clock low must be less than or equal to 1/fC.

(3)Value guaranteed by design and/or characterization, not 100% tested in production.

(4)Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.4. For multiple

bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes

programmed.

(5)It’s possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to

ensure reliable operation.

HM25Q128A

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