TMS320C80GF datasheet(49/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PP program-flow-control unit architecture (continued)

incrementer

ipa

ipe

Loop Controller 0

ls0

le0

Comparator

lr0

lc0

Loop Controller 1

Loop Controller 2

decr.

zero

lprs

Tag Comparators

Tag Registers

Present Bits

LRU Stack

Cache Controller

lctl

Loop Control

Instruction Decode

FAE Pipeline Control

Control Signal Generation

Instruction

Control

Signal

Instruction

Address

Figure 43. Program-Flow-Control Unit Block Diagram

PP address-unit architecture

The PP has both a local- and global-address unit which operate independently of each other. The address units

support twelve different addressing modes. In place of performing a memory access, either or both of the

address units can perform an address computation that is written directly to a PP register instead of being used

for a memory access. This address-unit arithmetic provides additional arithmetic operation to supplement the

data unit during compute-intensive algorithms. Figure 44 shows the address-out architecture.

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