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TMS320C80GF Scheda tecnica(PDF) 25 Page - Texas Instruments |
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TMS320C80GF Scheda tecnica(HTML) 25 Page - Texas Instruments |
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25 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 configuration (CONFIG) register (0x0002) The CONFIG register controls or reflects the state of certain options as shown in Figure 10. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E R T H X Reserved Type Reserved Release Reserved E R T H X Type Release Endian mode; 0 = big-endian, 1 = little-endian, read only PPData RAM round robin; 0 = fixed, 1 = variable, read / write TC PT round robin; 0 = variable, 1 = fixed, read / write. High priority MP events; 0 = disabled, 1 = enabled, read / write Externally initiated packet transfers; 0 = disabled, 1 = enabled, read / write Number of PPs in device, read only TMS320C80 version number Figure 10. CONFIG Register interrupt-enable (IE) register (0x0006) The IE register contains enable bits for each of the interrupts/traps as shown in Figure 11. The global-interrupt-enable (ie) bit and the appropriate individual interrupt-enable bit must be set in order for an interrupt to occur. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pe x4 x3 bp pb pc mi p3 p2 p1 p0 io mf x2 x1 ti f1 f0 fx fu fo fz fi ie pe x4 x3 bp pb pc mi p3 PP error External interrupt 4 (LINT4) External interrupt 3 (EINT3) Bad packet transfer Packet transfer busy Packet transfer complete Message (MP self) interrupt PP3 message interrupt p2 p1 p0 io mf x2 x1 ti PP2 message interrupt PP1message interrupt PP0 message interrupt Integer overflow Memory fault External interrupt 2 (EINT2) External interrupt 1 (EINT1) MP timer interrupt f1 f0 fx fu fo fz fi ie Frame-timer 1 interrupt Frame-timer 0 interrupt Floating-point inexact Floating-point underflow Floating-point overflow Floating-point divide-by-zero Floating-point invalid Global-interrupt enable Figure 11. IE Register interrupt-pending (INTPEN) register (0x0004) The bits in INTPEN register show the current state of each interrupt/trap. Pending interrupts do not occur unless the ie bit and corresponding interrupt-enable bit are set. Software must write a 1 to the appropriate INTPEN bit to clear an interrupt. Figure 12 shows the INTPEN register locations. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pe x4 x3 bp pb pc mi p3 p2 p1 p0 io mf x2 x1 ti f1 f0 fx fu fo fz fi Figure 12. INTPEN Register |
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