TMS320C80GF datasheet(15/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions

TERMINAL

DESCRIPTION

NAME

TYPE†

DESCRIPTION

LOCAL MEMORY INTERFACE

A31 – A0

Address bus. A31 – A0 output the 32-bit byte address of the external memory cycle. The address can be

multiplexed for DRAM accesses.

AS2 – AS0

Address-shift selection. AS2 – AS0 determine how the column address appears on the address bus. Eight

shift values are supported, including zero.

BS1 – BS0

Bus-size selection. BS1 – BS0 indicate the bus size of the memory or other device being accessed, allowing

dynamic bus sizing for data buses less than 64-bits wide.

CT2 – CT0

Cycle-timing selection. CT2 – CT0 signals determine the timing of the current memory access.

D63 – D0

I/O

Data bus. D63 – D0 transfer up to 64 bits of data per memory cycle into or out of the ’C80.

DBEN

Data-buffer enable. DBEN drives the active-low output-enables of bi-directional transceivers that can be

used to buffer input and output data on D63 – D0.

DDIN

Data-direction indicator. DDIN indicates the direction of the data that passes through the transceivers. When

DDIN is low, the transfer is from external memory into the ’C80.

FAULT

Fault. FAULT is driven low by external circuitry to inform the ’C80 that a fault has occurred on the current

memory row-access.

PS3 – PS0

Page-size indication. PS3 – PS0 indicate the page size of the memory device(s) being accessed by the

current cycle. The ’C80 uses this information to determine when to begin a new row-access.

READY

Ready. READY indicates that the external device is ready to complete the memory cycle. READY is driven

low by external circuitry to insert wait states into a memory cycle.

Row latch. The high-to-low transition of RL can be used to latch the valid 32-bit byte address that is present

on A31 – A0.

RETRY

Retry. RETRY is driven low by external circuitry to indicate that the addressed memory is busy. The ’C80

memory cycle is rescheduled.

STATUS5 – STATUS0

Status code. At row time, STATUS5 – STATUS0 indicate the type of cycle being performed. At column time,

they identify the processor and type of request that initiated the cycle.

UTIME

User-timing selection. UTIME causes the timing of RAS and CAS / DQM7 – CAS / DQM0 to be modified so

that custom memory timings can be generated. During reset, UTIME selects the endian mode in which the

’C80 operates.

DRAM, VRAM, AND SDRAM CONTROL

CAS / DQM7 –

CAS / DQM0

Column-address strobes. CAS / DQM7 – CAS / DQM0 drive the CAS inputs of DRAMs and VRAMs, or the

DQM input of SDRAMs. The eight strobes provide byte-write access to memory.

DSF

Special function. DSF selects special VRAM functions such as block-write, load color register, split-register

transfer, and SGRAM block write.

RAS

Row-address strobe. RAS drives the RAS inputs of DRAMs, VRAMs, and SDRAMs.

TRG / CAS

Transfer / output enable or column-address strobe. TRG / CAS is used as an output-enable for DRAMs and

VRAMs, and also as a transfer-enable for VRAMs. TRG / CAS also drives the CAS inputs of SDRAMs.

Write enable. W is driven low before CAS during write cycles. W controls the direction of the transfer during

VRAM transfer cycles.

† I = input, O = output, Z = high impedance

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