TMS320C80GF datasheet(18/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

architecture

Figure 1 shows the major components of the ’C80: the master processor (MP), the parallel digital signal

processors (PPs), the transfer controller ( TC), the video controller ( VC), and the IEEE-1149.1 emulation

interface. Shared access to on-chip RAM is achieved through the crossbar. Crossbar connections are

represented by

. Each PP can perform three accesses per cycle through its local ( L ), global ( G ), and

instruction ( I ) ports. The MP can access two RAMs per cycle through its crossbar/data ( C / D ) and instruction

( I ) ports, and the TC can access one RAM through its crossbar interface. Up to 15 simultaneous accesses are

supported in each cycle. Addresses can be changed every cycle, allowing the crossbar matrix to be changed

on a cycle-by-cycle basis. Contention between processors for the same RAM in the same cycle is resolved by

a round-robin priority scheme. In addition to the crossbar, a 32-bit datapath exists between the MP and the TC

and VC. This allows the MP to access TC and VC on-chip registers that are memory mapped into the MP

memory space.

The ’C80 has a 4G-byte address space as shown in Figure 2. The lower 32M bytes are used to address internal

RAM and memory-mapped registers.

PP3

PP2

PP1

PP0

C/D

OCR

IEEE-

1149.1

(JTAG)

Figure 1. Block Diagram Showing Datapaths

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