TMS320C80GF datasheet(26/171 Pages) TI

26 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

floating-point status register (FPST) (0x0008)

FPST contains status and control information for the FPU as shown in Figure 13. Bits 17–21 are read/write

floating-point unit (FPU) control bits. Bits 22 – 26 are read/write accumulated status bits. All other bits show the

status of the last FPU instruction to complete and are read only.

destination

drm

opcode

dest

drm

opcode

Destination register value

Accumulated value invalid

Accumulated divide-by-zero

Accumulated overflow

Accumulated underflow

Accumulated inexact

Sequential mode select

Floating-point stall

Vector fast mode

Rounding mode

00 – nearest

10 – positive

∞

01 – zero

11 – negative

∞

Last opcode

The tenth MSB of exponent

The ninth MSB of exponent

Destination precision

00 – single float

10 – signed int

01 – double float

11 – unsigned int

Rounding mode

00 – nearest

10 – positive

∞

01 – zero

11 – negative

∞

Int multiply overflow

Invalid

Divide-by-zero

Overflow

Underflow

Inexact

Figure 13. FPSTS Register

PP error register (PPERROR) (0x000A)

The bits in the PPERROR register reflect parallel processor errors (see Figure 14). The MP can use these when

a PP error interrupt occurs to determine the cause of the error.

Reserved

PP#

h – PP halted

i – PP illegal instruction

f – PP fault type; 0 = icache, 1 = DEA

Figure 14. PPERROR Register

packet-transfer request register (PKTREQ) (0x000D)

PKTREQ controls the submission and priority of packet-transfer requests as shown in Figure 15. It also

indicates that a packet transfer is currently active.

Reserved

I – Immediate (urgent) priority selected

F – High (foreground) priority selected

S – Suspend packet transfer

Q – Packet transfer queued; read only

P – Submit packet-transfer

request

Figure 15. PKTREQ Register

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