TMS320C80GF datasheet(52/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PP instruction set (continued)

Table 10. Summary of Data-Unit Operations

Operation

Base set ALUs

Description

Perform an ALU operation specifying ALU function, 2 src and 1 dest operand, and operand routing. ALU function is one of

256 three-input Boolean operations or one of 17 arithmetic operations combined with one of 15 function modifiers.

Syntax

dst = [fmod] [ [[cond [.pro] ]] ] ALU_EXPRESSION

Examples

d6 = (d6 ^ d4) & d2

d3 = [nn.nv] d1 –1

Operation

EALU || ROTATE

Description

Perform an extended ALU (EALU) operation (specified in d0) with one of two data routings to the ALU and optionally write

the barrel rotator output to a second dest register. ALU Function is one of 256 Boolean or 256 arithmetic.

Syntax

dst1 = [ [[cond [.pro] ]] ] ealu (src2, [dst2 = ] [ [[cond]] src1 [[[n]] src1–1] \\ src3, [%] src4)

dst1 = [fmod] [ [[cond [.pro] ]] ] ealu (label:EALU_EXPRESSION [ || dst2 = [[cond]] src1 [ [[n]] src1–1] \\ src3])

Examples

d7 = [nn] ealu(d2, d6 = [nn] d3\\d1, %d4)

d3 = mzc ealu(mylabel: d4 + (d5\\d6 & %d7) || d1 = d5\\d6)

Operation

MPY || ADD

Description

Perform a 16x16 multiply with optional parallel add or subtract. Condition code applies to both multiply and add.

Syntax

dst2 = [sign] [ [[cond]] ] src3 * src4 [ || dst = [ [[cond[.pro] ]] ] src2 + src1 [ [[n]] src1 –1] ]

dst2 = [sign] [ [[cond]] ] src3 * src4 [ || dst = [ [[cond[.pro] ]] ] src2 – src1 [ [[n]] src1 –1] ]

Example

d7 = u d6 * d5 || d5 = d4 – d1

Operation

MPY || SADD

Description

Perform a 16x16 multiply with a parallel right-shift and add or subtract. Condition code applies to multiply, shift, and add.

Syntax

dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[ cond [.pro] ]] ] src2 + src1 [ [[n]] src1 –1] >> –d0

dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[ cond [.pro] ]] ] src2 – src1 [ [[n]] src1 –1] >> –d0

Examples

d7 = u d6 * d5 || d5 = d4 – d1 >> –d0

Operation

MPY || EALU

Description

Perform a multiply and an optional parallel EALU. Multiply can use rounding, scaling, or splitting features.

Syntax

Generic Form:

dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[cond [.pro] ]] ] ealu[f] (src2, src1 [ [[n]] src1 –1] \\ d0, %d0)

dst2 = [sign] [ [[cond]] ] src3 * src4 || ealu()

Explicit Form:

dst2 = [sign] [opt] [ [[cond]] ] src3 * src4 [<<dms] || dst1 = [fmod] [ [[cond [.pro] ]] ] ealu (label: EALU_EXPRESSION)

dst2 = [sign] [opt] [ [[cond]] ] src3 * src4 [<<dms] || ealu (label)

Examples

d7 = [p] d5 * d3 || d2 = [p] ealu(d1, d6\\d0, %d0)

; generic form

d2 = m d4 * d7 || d3 = ealu (mylabel: d3 + d2 >> 9)

; explicit form

Operation

divi

Description

Perform one iteration of unsigned divide algorithm. Generates one quotient bit per execution using iterative subtraction.

Syntax

dst1 = [ [[cond [.pro] ]] ] divi (src2, dst2 = [[cond]] src1 [ [[n]] src1 –1])

Examples

d3 = divi (d1, d2 = d2)

d3 = divi (d1, d2 = d3[n]d2)

Legend:

[ ]

Optional parameter extension

cond

Condition code

[[ ]]

Square brackets ([ ]) must be used

fmod

Function modifier

pro

Protect status bits

dms

Default multiply shift amount

Use 1s compliment of d0

sign

u = unsigned, s = signed

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