TMS320C80GF datasheet(70/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

TC functional block diagram (continued)

Src MUX and

Alignment

Request Queuing and Prioritization

Cache Buffer

Crossbar

Interface

Src

Controller

Dst

Controller

Packet Transfer

FIFO

Cache, VRAM, and

Refresh Controller

Dst MUX and

Alignment

External

Memory

Interface

Src Control

Registers

Dst Control

Registers

Requests

XPT

Requests

Host

Requests

Figure 52. TC Block Diagram

TC registers

The TC contains four on-chip memory-mapped registers accessible by the MP. TC registers are shown in

Figure 53.

refresh control (REFCNTL) register (0x01820000)

The REFCNTL register controls refresh cycles.

RPARLD

REFRATE

RPARLD

Refresh Pseudo-Address Reload Value

REFRATE

Refresh Interval (in clock cycles)

Figure 53. REFCNTL Register

packet-transfer minimum (PTMIN) register (0x01820004)

The PTMIN register determines the minimum number of cycles that a packet transfer executes before being

suspended by a higher priority packet transfer. Figure 54 shows the PTMIN register.

PTMIN

Figure 54. PTMIN Register

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