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TMS320C80GF Scheda tecnica(PDF) 76 Page - Texas Instruments

Il numero della parte TMS320C80GF
Spiegazioni elettronici  DIGITAL SIGNAL PROCESSOR
PDF  171 Pages
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Produttore elettronici  TI [Texas Instruments]
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TMS320C80GF Scheda tecnica(HTML) 76 Page - Texas Instruments

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TMS320C80
DIGITAL SIGNAL PROCESSOR
SPRS023B – JULY 1994 – REVISED OCTOBER 1997
73
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
address multiplexing
To support various RAM devices, the TMS320C80 can provide multiplexed row and column addresses on its
address bus. A full 32-bit address is always output at row time. The alignment of column addresses is configured
by the value input on the AS[2:0] pins at row time (see Figure 59).
A[31:0] Pins
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Row Time
A[31:0] Pins
AS [2:0]
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Column Time
Figure 59. Address Multiplexing
dynamic bus sizing
The ’C80 supports data bus sizes of 8, 16, 32, or 64 bits as shown in Table 31. The value input on the BS[1:0]
pins at row time indicates the bus size of the addressed memory. This determines the maximum number of bytes
which the ’C80 can transfer during each column access. If the number of bytes to be transferred exceeds the
bus size, multiple accesses are performed automatically to complete the transfer.
Table 31. Bus Size Selection
BS[1:0]
BUS SIZE
0 0
8 bits
0 1
16 bits
1 0
32 bits
1 1
64 bits
The selected bus size also determines which portion of the data bus is used for the transfer. For 64-bit memory,
the entire data bus is used. For 32-bit memory, D[31:0] are used in little-endian mode and D[63:32] are used
in big-endian mode. 16-bit buses use D[15:0] and D[63:48] and 8-bit buses use D[7:0] and D[63:56] for little-
and big-endian modes, respectively. The ’C80 always aligns data to the proper portion of the bus and activates
the appropriate CAS / DQM strobes to ensure that only valid bytes are transferred.



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