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MCP47FXB2XT-EST Scheda tecnica(PDF) 109 Page - Microchip Technology

Il numero della parte MCP47FXB2XT-EST
Spiegazioni elettronici  8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL Digital-to-Analog Converters with I짼C Interface
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MCP47FXB2XT-EST Scheda tecnica(HTML) 109 Page - Microchip Technology

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 2020 Microchip Technology Inc.
DS20006368A-page 109
MCP47FXBX4/8
APPENDIX B: I2C SERIAL
INTERFACE
This I2C interface is a two-wire interface that allows
multiple devices to be connected to this two-wire bus.
Figure B-1 shows a typical I2C interface connection.
FIGURE B-1:
TYPICAL I2C INTERFACE.
B.1
Overview
A device that sends data onto the bus is defined as
transmitter, and a device receiving data is defined as
receiver. The bus must be controlled by a master
device which generates the Serial Clock (SCL),
controls the bus access and generates the Start and
Stop conditions. Devices that do not generate a serial
clock work as slave devices. Both master and slave
can operate as transmitter or receiver, but the master
device
determines
which
mode
is
activated.
Communication is initiated by the master (micro-
controller), which sends the Start bit followed by the
slave address byte. The first byte transmitted is always
the slave address byte, which contains the device
code, the address bits and the R/W bit.
The I2C interface specifies different communication bit
rates. These are referred to as Standard, Fast or High-
Speed modes. The MCP47FXBX4/8 supports these
three modes. The clock rates (bit rate) of these modes
are:
• Standard mode: up to 100 kHz (kbit/s)
• Fast mode: up to 400 kHz (kbit/s)
• High-Speed mode (HS mode): up to 3.4 MHz
(Mbit/s)
The I2C protocol supports two addressing modes:
• 7-bit slave addressing
• 10-bit slave addressing (allows more devices on
the I2C bus)
Only 7-bit slave addressing will be discussed in this
section.
The I2C serial protocol allows multiple master devices
on the I2C bus. This is referred to as Multi-master. For
this, all master devices must support Multi-master
operation. In this configuration, all master devices mon-
itor their communication. If they detect that they wish to
transmit a bit that is a logic high but is detected as a
logic low (some other master device driving), they “get
off” the bus. That is, they stop their communication and
continue to listen to determine if the communication is
directed towards them.
The I2C serial protocol only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. For details on the
frame content (commands/data), refer to Section 7.0
“I2C Device Commands”.
The I2C serial protocol defines some commands called
“General Call Addressing”, which allows the master
device to communicate to all slave devices on the I2C
bus.
SCL
SCL
Slave
SDA
SDA
Master
Typical I2C Interface Connections
Other Devices
Note:
Refer
to
the
NXP
Specification
#UM10204, Rev. 03 19 June 2007
document for more details on the I2C
specifications.



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