MCP47FXB2XT-EST datasheet(112/124 Pages) MICROCHIP

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MCP47FXBX4/8

DS20006368A-page 112

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B.3.4

SLOPE CONTROL

As the device transitions from HS mode to FS mode,

the slope control parameter changes from the HS

specification to the FS specification.

For FS and HS modes, the device has a spike suppres-

sion and a Schmitt Trigger at SDA and SCL inputs.

B.3.5

DEVICE ADDRESSING

The I2C slave address control byte is the first byte

received following the Start condition from the master

device. This byte has seven bits to specify the slave

address and the Read/Write control bit.

Figure B-9 shows the I2C slave address byte format,

which contains the seven address bits and a

Read/Write (R/W) bit.

FIGURE B-9:

I2C SLAVE ADDRESS

CONTROL BYTE.

B.3.6

HS MODE

The I2C specification requires that a High-Speed mode

device be activated to operate in HS (3.4 Mbit/s) mode.

This is done by the master sending a special address

byte following the Start bit. This byte is referred to as

the High-Speed Master Mode Code (HSMMC).

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

The master code is sent as follows:

Start condition (S)

High-Speed Master Mode Code (0000 1XXX),

The XXX bits are unique to the HS mode master.

No Acknowledge (A)

After switching to the HS mode, the next transferred

byte is the I2C control byte, which specifies the device

to communicate with and any number of data bytes

plus acknowledgments. The master device can then

either issue a Repeated Start bit to address a different

device (at high speed) or a Stop bit to return to

fast/standard bus speed. After the Stop bit, any other

master device (in a Multi-master system) can arbitrate

for the I2C bus.

See Figure B-10 for an illustration of the HS mode com-

mand sequence.

For more information on the HS mode, or other I2C

modes, refer to the “NXP I2C Specification”.

B.3.6.1

Slope Control

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

clock modes of the interface.

B.3.6.2

Pulse Gobbler

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

FIGURE B-10:

HS MODE SEQUENCE.

Start Bit

Read/Write Bit

Address Byte

R/W ACK

Acknowledge Bit

7-bit Slave Address

‘0 0 0 0 1 X X X’b

Slave Address

A/A

Data

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

R/W

P = Stop bit (Stop condition terminates HS mode)

F/S mode

HS mode

HS mode continues

F/S mode

Slave Address R/W

HS Select Byte

Control Byte

Command/Data Byte(s)

Control Byte

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