PIMXRT406LCAF4A datasheet(40/100 Pages) NXP

40 / 100 page

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

Electrical characteristics

Figure 14. Trace data specifications

4.5

External memory interface

The following sections provide information about external memory interfaces.

4.5.1

SEMC specifications

The following sections provide information on SEMC interface.

Measurements are with a load of 15 pf and an input slew rate of 1 V/ns.

4.5.1.1

SEMC output timing

There are ASYNC and SYNC mode for SEMC output timing.

4.5.1.1.1

SEMC output timing in ASYNC mode

Table 31 shows SEMC output timing in ASYNC mode.

Table 31. SEMC output timing in ASYNC mode

Symbol

Parameter

Min.

Max.

Unit

Comment

Frequency of operation

—

133

MHz

TCK

Internal clock period

7.5

—

TAVO

Address output valid time

—

These timing parameters

apply to Address and ADV#

for NOR/PSRAM in ASYNC

mode.

TAHO

Address output hold time

(TCK - 2) 1

1 Address output hold time is configurable by SEMC_*CR0.AH. AH field setting value is 0x0 in above table. When AH is set

with value N, TAHO min time should be ((N + 1) x TCK). See the i.MX RT1020 Reference Manual (IMXRT1020RM) for more

detail about SEMC_*CR0.AH register field.

—ns

TADVL

ADV# low time

(TCK - 1) 2

TDVO

Data output valid time

—

These timing parameters

apply to Data/CLE/ALE and

WE# for NAND, apply to

Data/DM/CRE for

NOR/PSRAM, apply to

Data/DCX and WRX for DBI

interface.

TDHO

Data output hold time

(TCK - 2) 3

—ns

TWEL

WE# low time

(TCK - 1) 4

ARM_TRACE_CLK

ARM_TRACE0-3

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