PIMXRT406LCAF4A datasheet(66/100 Pages) NXP

66 / 100 page

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

Electrical characteristics

4.8.3.3

SDR50/SDR104 AC timing

Figure 41 depicts the timing of SDR50/SDR104, and Table 58 lists the SDR50/SDR104 timing

characteristics.

Figure 41. SDR50/SDR104 timing

Table 58. SDR50/SDR104 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

5.0

—

SD2

Clock Low Time

tCL

0.46 x tCLK

0.54 x tCLK

SD3

Clock High Time

tCH

0.46 x tCLK

0.54 x tCLK

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4

uSDHC Output Delay

tOD

–3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

–1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6

uSDHC Input Setup Time

tISU

2.5

—

SD7

uSDHC Input Hold Time

tIH

1.5

—

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1

1Data window in SDR104 mode is variable.

SD8

Card Output Data Window

tODW

0.5 x tCLK

—ns

SCK

4-bit output from uSDHC to card

4-bit input from card to uSDHC

SD8

SD7

SD6

SD4/SD5

SD2

SD3

SD1

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