PIMXRT406LCAF4A datasheet(96/100 Pages) NXP

96 / 100 page

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

Revision history

Table 86 provides a revision history for this data sheet.

Table 86. i.MX RT1020 data sheet document revision history

Rev.

Number

Date

Substantive Change(s)

Rev. 2

03/2021

• Updated the M7 core, external memory, and ADC descriptions in the Section 1.1, Features

• Updated the Figure 1, "Part number nomenclature—i.MX RT10XX family"

• Updated the baud rates of LPUART and frequency of RTC OSC in the Table 3 i.MX RT1020 modules

list

• Updated the remarks of TEST_MODE in the Table 4, Special signal considerations

• Added system and bus frequencies in the Table 11, Operating ranges; updated the junction

temperature descriptions in the Table 11, Operating ranges

• Updated the test conditions and max current of DCDC_IN in the Table 13, Maximum supply currents

• Added a note in the Section 4.2.1.1, Power-up sequence

• Updated the value of reference clock in the Table 18, Ethernet PLL’s electrical parameters

• Added the high-level and low level output current in the Table 22, Single voltage GPIO DC parameters

• Updated the frequency of operation and internal clock period in the Table 31, SEMC output timing in

ASYNC mode

• Updated the frequency of operation and internal clock period in the Table 32, SEMC output timing in

SYNC mode

• Added a footnote for GPIO_EMC_04 in the Table 83, 20 x 20 mm functional contact assignments and

Table 85, 14 x 14 mm functional contact assignments

Rev. 1

04/2019

• Added analog descriptions in the Section 1.1, Features

• Added ADC channel number in the Table 1, The comparison between 100 LQFP and 144 LQFP

package

• Updated the RT website link in the Section 1.2, Ordering information

• Updated the ADC descriptions in the Figure 2, "i.MX RT1020 system block diagram"

• Updated the RAM size, SNVS descriptions, and USB descriptions in the Table 3, i.MX RT1020

modules list

• Updated the on-chip termination values of JTAG_TCK and JTAG_MOD in the Table 5, JTAG controller

interface summary

• Updated the maximum values of VDD_SOC_IN in the Table 8, Absolute maximum ratings

• Removed the USB_OTG2_VBUS from the Table 8, Absolute maximum ratings, Table 11, Operating

ranges, and Section 4.2.1.1, Power-up sequence

• Changed 528 MHz PLL to System PLL in the Table 17, System PLL’s electrical parameters

• Changed 480 MHz PLL to USB PLL in the Table 19, USB PLL’s electrical parameters

• Updated the Section 4.8.1, LPSPI timing parameters

• Added the Figure 32, "Minimum Sample Time Vs Ras (Cas = 2pF)", Figure 33, "Minimum Sample

Time Vs Ras (Cas = 5 pF)", and Figure 34, "Minimum Sample Time Vs Ras (Cas = 10 pF)" in the

Section 4.7.2, A/D converter

Rev. 0.1

07/2018

• Updated the Table 14, Low power mode current and power consumption

• Added the Section 4.4.4, Debug trace timing specifications

Rev. 0

06/2018

• Initial version

PIMXRT406LCAF4A Scheda tecnica(PDF) 96 Page - NXP Semiconductors

PIMXRT406LCAF4A Scheda tecnica(HTML) 96 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Scheda tecnica Scarica

Link URL