ADL6317ACCZ-R7 datasheet(14/38 Pages) AD

14 / 38 page

ADL6317

Data Sheet

Rev. B | Page 14 of 38

THEORY OF OPERATION

The ADL6317 is a highly integrated transmit VGA used to

interface an RF DAC to the power amplifier in a transmitter.

The ADL6317 targets high dynamic range multicarrier

transmitter designs.

The ADL6317 offers multiple gain control options with an

integrated 20.5 dB VVA, on-chip DAC control or external

voltage control, a high linearity amplifier, an RF DSA with a

15.5 dB attenuation range in 0.5 dB steps, followed by the

second stage high linearity amplifier.

Putting all the building blocks of the ADL6317 together, the

signal path through the device starts with differential inputs

converted to singled-ended by the integrated balun and this

single-ended signal is then quadrature coupled by the internal

quadrature hybrid.

Next, the integrated VVA, Amplifier 1, DSA, and Amplifier 2

optimize the RF signal amplitude for performance before the

RF signal passes through the output quadrature hybrid. All the

integrated building blocks of the ADL6317 are programmable via

the SPI.

RF INPUT BALUN WITH DAC INTERFACE

NETWORK

The ADL6317 converts a single-channel, 50 Ω, input differen-

tial signal to a single-ended signal via the integrated balun.

Wideband matching allows the DAC to operate over a

frequency range from 1500 MHz to 3000 MHz, and a bias tee is

included to provide dc bias for the RF DAC.

QUADRATURE HYBRID

Integrated quadrature hybrids at the RF input and RF output

allow wideband performance gain and match with a low input

and output reflection coefficient to the RF DAC and PA.

RF SIGNAL CHAIN

The RF path includes a 20.5 dB VVA, the first stage of the fixed

gain amplifier, a 15.5 dB DSA, and the second stage of the fixed

gain amplifier (see Figure 38). The ADL6317 has two modes of

control of the VVA attenuation: internal analog control using an

integrated 12-bit DAC and external analog control. For internal

control, use Register 0x104, Bits[3:0] and Register 0x103, Bits[7:0]

to set the attenuation. The digital bits are double buffered to

avoid major carrier glitch. For this reason, Register 0x104 must

be written before Register 0x103. For external analog control of

the VVA, a control voltage is applied to the VVA_ANALOG pin

(Pin 30). Sample register writes for VVA control are shown in

Figure 38.

Table 7. Register Writes for the Control of VVA

Addres

Bits

Settings

Description

0x105

[1:0]

DAC to VVA

VVA_ANALOG (Pin 30) to VVA

0x104

[3:0]

User

defined

12-bit DAC code to set VVA

attenuation; first, write to

then to Register 0x103, Bits[7:0]

0x103

[7:0]

User

defined

Next, the fixed gain amplifier is used in a quadrature balanced

configuration. The DSA provides a 15.5 dB range with 0.5 dB

step resolution. The digital 5-bit DSA attenuation control is found

in Bits[4:0] of Register 0x102 and Register 0x112. Finally, the

second stage fixed gain amplifier is used in a quadrature

balanced configuration.

DAC

VVA_ANALOG

VVA CONTROL

VVA

AMP

POWER UP

DEFAULT

IN GRAY

VVA_SRC

DSA

QUADRATURE

HYBRID

AMP

VVA_ATTEN, BITS[11:0] =

AND

BALUN

QUADRATURE

HYBRID

Figure 38. RF Signal Chain

ADL6317ACCZ-R7 Scheda tecnica(PDF) 14 Page - Analog Devices

ADL6317ACCZ-R7 Scheda tecnica(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Scheda tecnica Scarica

Link URL