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ADL6317

Data Sheet

Rev. B | Page 18 of 38

SERIAL PORT INTERFACE (SPI)

The SPI of the ADL6317 allows the user to configure the device

for specific functions or operations via a 4-wire SPI port. This

interface provides users with added flexibility and customization.

The serial port interface consists of four control lines: SCLK, SDI,

SDO, and CS. The timing requirements for the SPI port are

shown in Table 3.

The ADL6317 protocol consists of a read/write bit, six chip select

ID bits, and nine register address bits, followed by eight data bits.

Both the address and data fields are organized with the MSB

first and end with the LSB by default.

The ADL6317 input logic level for the write cycle is with a 1.8 V

logic level (see the digital logic parameter in Table 2).

On a read cycle, the SDO is configurable for 1.8 V (default) or

3.3 V output levels by setting SPI_1P8_3P3_CTRL bit

(Register 0x121, Bit 4).

Multiple Chip Operation to Share SPI Bus

Multiple ADL6317 devices, up to four, can be addressed using

the same 4-wire SPI, which means no extra CS line for each

device. For this capability, the chip ID bits of the ADL6317 are

reserved as the chip ID (see the SPI interface port as shown in

Figure 2).

The ADL6317 ignores any writes to addresses where the six

MSBs are not equal to the chip ID, with the exception of

writes for these registers regardless of the six MSBs of the

address.

The ADL6317 only accepts reads for addresses where the six

MSBs are equal to the chip ID, including Register 0x000 to

Figure 42 shows how to configure the chip ID and the CS5 and

CS4 pins to share a 4-wire SPI. The CS5 and CS4 settings are

shown in gray in Figure 42.

ADL6317

DEVICE 2

CHIP ID = 100000

4-WIRE SPI

CS, SDI, SDO, SCLK

CS5 PIN

1.8V

CS4 PIN

ADL6317

DEVICE 0

CHIP ID = 000000

CS5 PIN

CS4 PIN

ADL6317

DEVICE 3

CHIP ID = 110000

CS5 PIN

1.8V

CS4 PIN

1.8V

ADL6317

DEVICE 1

CHIP ID = 010000

CS5 PIN

CS4 PIN

Figure 42. Multiple Chip Configuration to Share SPI Bus

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