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ADL6317ACCZ-R7 Scheda tecnica(PDF) 15 Page - Analog Devices |
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ADL6317ACCZ-R7 Scheda tecnica(HTML) 15 Page - Analog Devices |
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15 / 38 page  Data Sheet ADL6317 Rev. B | Page 15 of 38 BASIC CONNECTIONS 10PF 0.1µF 270PF ADL6317 RFOUT VDAC C9 C12 C5 R11 560Ω U1 VVA_ANALOG V50AMP1 V50AMP2 SDO 1 3 4 34 32 23 15 13 17 5 30 AGND 0.1µF C14 AGND AGND 10pF 0.1µF C8 C11 1µF C6 0.1µF C13 AGND AGND AGND AGND AGND TXEN SDI CS MUXOUT VVA_ANALOG RFOUT V50AMP2 V33FUSE V50AMP1 VDAC IN_P IN_N 28 IN_N 33 SCLK SDO SCLK 35 SDI CS TXEN 36 37 V33FUSE MUXOUT CS5 CS4 29 AGND IN_P AGND AGND Figure 39. Basic Connections Table 8. Basic Connections Functional Blocks Pin No. Mnemonic Description Basic Connection 5 V 13, 17 V50AMP1, V50AMP2 Amplifier analog supply voltage, 5 V Decouple these pins via 10 pF and 0.1 µF capacitors to ground. Ensure that the decoupling capacitors are located close to the pins. Decoupling 15 V33FUSE 3.3 V LDO regulator decoupling Decouple this pin via 0.1 µF and 1 µF capacitors to ground. Ensure that the decoupling capacitors are located close to the pin. RF Inputs 5 VDAC Supply voltage for external RF DAC VDAC can be left open during operation without the RF DAC. 3, 4 IN_N, IN_P Differential RF inputs Connect the IN_N and IN_P pins to an RF DAC or transceiver output in differential configuration. VVA 30 VVA_ANALOG External VVA control voltage input Voltage input pin to control VVA attenuation. RF Output 23 RFOUT Single-ended RF output Connect RF output to power meter, network analyzer, noise figure meter, or spectrum analyzer. Serial Port 33 SDO SPI data output 1.8 V to 3.3 V tolerant logic levels. 34 SCLK SPI clock 1.8 V to 3.3 V tolerant logic levels. 35 SDI SPI data input 1.8 V to 3.3 V tolerant logic levels. 36 CS Chip select active low 1.8 V to 3.3 V tolerant logic levels. Auxiliary Mux 32 MUXOUT Mux output Connect mux output to multimeter, oscilloscope, or spectrum analyzer. Chip Selection 28, 29 CS4, CS5 Chip selection Connect these pins to ground. Mode Control 37 TXEN Amplifier enable, DSA attenuation, and trim value selection 1.8 V to 3.3 V tolerant logic levels. Ground 1, 2, 6 to 9, 12, 14, 19 to 22, 24 to 26, 31, 38 GND Ground Connect these pins to the ground of the PCB. Exposed Pad Not applicable EPAD1, EPAD2 Exposed pads The exposed thermal pads are on the bottom of the package. Solder the exposed pads to the PCB ground. EPAD1 and EPAD2 are internally connected to each other. |
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