 |
Motore di ricerca datesheet componenti elettronici |
|
|
Motore di ricerca datesheet componenti elettronici |
|
ADL6317ACCZ-R7 Scheda tecnica(PDF) 16 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADL6317ACCZ-R7 Scheda tecnica(HTML) 16 Page - Analog Devices |
|
|
16 / 38 page  ADL6317 Data Sheet Rev. B | Page 16 of 38 PROGRAMMABILITY GUIDE Viewing the register map at the highest level, the registers are subdivided into the major functional blocks, as shown in Table 9. See the Register Summary section for a complete list of all the registers on the ADL6317. Table 9. Memory Map Functional Groups Register Address Functional Blocks 0x000 to 0x011 Analog Devices, Inc., SPI configuration 0x100 to 0x101, 0x106 Signal path enable 0x103 to 0x105 VVA source, VVA attenuation 0x10B, 0x11B Amplifier 2 optimization 0x102, 0x107 to 0x10A DSA attenuation, amplifier enable, amplifier trim, TXEN = 0 mode 0x112, 0x117 to 0x11A DSA attenuation, amplifier enable, amplifier trim, TXEN = 1 mode 0x120 to 0x121 Auxiliary mux selection, SPI supply control 0x127 to 0x129 ADC clock, temperature readback 0x146 to 0x148 VVA and DSA attenuation readback SIGNAL PATH MODES The ADL6317 has two signal path modes. This feature allows two predefined modes of operation to be controlled by TXEN, a real- time external pin with no SPI latency. Table 10 shows the hardware configuration to select the desired mode. Table 10. Mode Selection and Setup Registers TXEN (Pin 37) Mode Enable, Setup Register 0 TXEN = 0 0x102, 0x107 to 0x10A 1 TXEN = 1 0x112, 0x117 to 0x11A The controls of each mode of operation reside in a designated subsection of the register map. Each operational mode includes individual control of the enables of the amplifier blocks, DSA attenuation, and power mode. Control of these functions reside in Register 0x102 and Register 0x107 to Register 0x10A for TXEN = 0 mode, or Register 0x112 and Register 0x117 to Register 0x11A for TXEN = 1 mode. The specific mode selected by the logic level on the TXEN pin (Pin 37) determines the state of the registers (see Table 11). Table 11. Control Registers for the Modes Register Address Mode Function Block 0x102 TXEN = 0 DSA attenuation 0x112 TXEN = 1 DSA attenuation 0x107 TXEN = 0 Amplifier 1 optimization 0x117 TXEN = 1 Amplifier 1 optimization 0x108 TXEN = 0 Amplifier 1 enable 0x118 TXEN = 1 Amplifier 1 enable 0x109 TXEN = 0 Amplifier 2 optimization 0x119 TXEN = 1 Amplifier 2 optimization 0x10A TXEN = 0 Amplifier 2 enable 0x11A TXEN = 1 Amplifier 2 enable Signal Path Enable The signal path enable bits are located in Register 0x100, Register 0x108, Register 0x118, Register 0x10A, and Register 0x11A. Figure 40 shows a breakdown of the individual blocks that the particular enable bit controls. AUXILIARY MUX CONTROL The ADL6317 has multiple auxiliary mux control blocks that allow various modes of operation and monitoring points (see Figure 41 and Table 12). DAC CS5 MUXOUT VVA_ANALOG ANALOG MUX TEMPERATURE SENSOR 3.3V LDO 1.8V SPI LDO ADC GND GND SERIAL PORT INTERFACE FUSE BLOCK AMP2 AMP2 AMP1 AMP1 VVA TXEN CS SDI SCLK SDO GND GND GND GND IN_N IN_P VDAC GND GND GND GND 1: DAC_EN 2: AMUX_BG_EN 3: ADC_EN 4: DSA_EN 5: VVA_EN 6: AMP1_EN_x1 7: AMP2_EN_x1 V50AMP1 V33FUSE V50AMP2 GND GND RFOUT GND GND GND GND CS4 VVA DSA DSA 3 1 5 2 4 6 7 1x = 0 (LOGIC LEVEL = 0) , 1 (LOGIC LEVEL = 1) ON TXEN PIN (PIN 37) Figure 40. Signal Path Enable Block Diagram |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
