ADL6317ACCZ-R7 datasheet(17/38 Pages) AD

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Data Sheet

ADL6317

Rev. B | Page 17 of 38

(REGISTER 0x104, BITS[ 3:0], REGISTER 0x103, BITS[7:0]) = VVA_ATTEN, BITS[11:0]

PIN 30

DAC

VVA_ANALOG

VVA_SRC = REGISTER 0x105, BITS[1:0]

ADC INPUT

ADC CLOCK

POWER-UP DEFAULTS IN GRAY

1.8V LDO OUTPUT

MUXOUT

PIN 32

AD_COUT, BITS[7:0]

VVA_CTRL

ADC INPUT

3.3V LDO OUTPUT

AMUX_3_SEL = REGISTER 0x120, BITS[6:4]

AMUX_1_SEL = REGISTER 0x120, BITS[2:0]

AMUX_2_SEL = REGISTER 0x120, BIT 3

PTAT

000

002

001

ADC

Figure 41. Auxiliary Mux Block Diagram

Table 12. Auxiliary Mux Programming Guide

Bit Name

Setting

Description

AMUX_3_SEL

ADC input, VVA_CTRL, and ADC clock selection on mux. VVA_CTRL is the

internal control voltage signal to control VVA attenuation.

000

VVA_CTRL.

001

ADC input.

010

ADC clock.

011

Not used.

100

Not used.

101

Not used.

110

Not used.

111

Not used.

AMUX_2_SEL

ADC input selection.

PTAT to ADC input.

VVA_CTRL to ADC input.

AMUX_1_SEL

Select mux output.

000

PTAT.

001

Output of AMUX_3_SEL.

010

1.8 V LDO output.

011

3.3 V LDO output.

100

GND.

101

GND.

110

Not used.

111

Not used.

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