ADSP-SC596 datasheet(71/134 Pages) AD

71 / 134 page

Rev. PrD

Page 71 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Link Ports (LPs)

In LP receive mode, the LP clock is supplied externally and is called fLCLKREXT, therefore the period can be represented by

In LP transmit mode, the programmed LP clock (fLCLKTPROG) frequency in megahertz is set by the following equation where VALUE is a

field in the LP_DIV register that can be set from 1 to 255:

In the case where VALUE = 0, fLCLKTPROG = fCDU_CLKO8. For all settings of VALUE, the following equation is true:

Calculation of the link receiver data setup and hold relative to the link clock is required to determine the maximum allowable skew that

can be introduced in the transmission path length difference between LPx_Dx and LPx_CLK. Setup skew is the maximum delay that can

be introduced in LPx_Dx relative to LPx_CLK (setup skew = tLCLKTWH minimum – tDLDCH – tSLDCL). Hold skew is the maximum delay

that can be introduced in LPx_CLK relative to LPx_Dx (hold skew = tLCLKTWL minimum – tHLDCH – tHLDCL). See Table 40 for LP transmit

timing.

Table 39. LPs—Receive1

1 Specifications apply to LP0 and LP1.

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

fLCLKREXT

LPx_CLK Frequency

125

MHz

tSLDCL

Data Setup Before LPx_CLK Low

1.5

tHLDCL

Data Hold After LPx_CLK Low

1.4

tLCLKEW

LPx_CLK Period2

2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external

LPx_CLK ideal maximum frequency, see the fLCLKRTEXT specification in Table 22.

tLCLKREXT – 1

tLCLKRWL

LPx_CLK Width Low2

0.5 × tLCLKREXT

tLCLKRWH

LPx_CLK Width High2

0.5 × tLCLKREXT

Switching Characteristic

tDLALC

LPx_ACK Low Delay After LPx_CLK Low3

3 LPx_ACK goes low with tDLALC relative to rise of LPx_CLK after first byte, but does not go low if the link buffer of the receiver is not about to fill.

1.5 × tCDU_CLKO8 + 4

2.5 × tCDU_CLKO8 + 12

tLCLKREXT

fLCLKREXT

---------------

fLCLKTPROG

fCDU_CLKO8

VALUE





----------------------

tLCLKTPROG

fLCLKTPROG

------------------

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