ADSP-SC596 datasheet(26/134 Pages) AD

26 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 26 of 134

May 2022

JTG_TMS

Input

JTAG Mode Select. JTAG test access port mode select.

JTG_TRST

Input

JTAG Reset. JTAG test access port reset.

LP_ACK

InOut

Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output.

When the link port is configured as a transmitter, ACK is an input.

LP_CLK

InOut

Clock. When the link port is configured as a receiver, CLK is an input. When the link port is configured

as a transmitter, CLK is an output.

LP_D[n]

InOut

Data n Data bus. Input when receiving, output when transmitting.

MLB_CLK

Input

Single Ended Clock.

MLB_CLKN

Input

Differential Clock (–).

MLB_CLKOUT

Output

Single Ended Clock Out.

MLB_CLKP

Input

Differential Clock (+).

MLB_DAT

InOut

Single Ended Data.

MLB_DATN

InOut

Differential Data (–).

MLB_DATP

InOut

Differential Data (+).

MLB_SIG

InOut

Single Ended Signal.

MLB_SIGN

InOut

Differential Signal (–).

MLB_SIGP

InOut

Differential Signal (+).

OSPI_CLK

Output

Clock Output. SPI master clock output.

OSPI_D2

InOut

Data 2. Transfers serial data in quad and octal mode.

OSPI_D3

InOut

Data 3. Transfers serial data in quad and octal mode.

OSPI_D4

InOut

Data 4. Transfers serial data in octal mode.

OSPI_D5

InOut

Data 5. Transfers serial data in octal mode.

OSPI_D6

InOut

Data 6. Transfers serial data in octal mode.

OSPI_D7

InOut

Data 7. Transfers serial data in octal mode.

OSPI_DQS

Input

Data Strobe. Data strobe input from an external flash device.

OSPI_MISO

InOut

Master In, Slave Out. Transfers serial data. Operates in the same direction as OSPI_MOSI in dual, quad,

and octal modes.

OSPI_MOSI

InOut

Master Out, Slave Input. Transfers serial data. Operates in the same direction as SPI_MISO in dual,

quad, and octal modes.

OSPI_SEL[n]

Output

Slave Select Output n. Used in master mode to enable the desired slave.

PPI_CLK

InOut

Clock. Input in external clock mode, output in internal clock mode.

PPI_D[nn]

InOut

Data n. Bidirectional data bus.

PPI_FS1

InOut

Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI chapter of the

ADSP-SC595/SC596/SC598 SHARC+ Processor Hardware Reference for more details.

PPI_FS2

InOut

Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI chapter of the

ADSP-SC595/SC596/SC598 SHARC+ Processor Hardware Reference for more details.

PPI_FS3

InOut

Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI chapter of the

ADSP-2159x/ADSP-SC59x SHARC+ Processor Hardware Reference for more details.

P_[nn]

InOut

Position n. General-purpose input/output. See the GP Ports chapter of the

ADSP-SC595/SC596/SC598 SHARC+ Processor Hardware Reference for more details.

SPI_CLK

InOut

Clock. Input in slave mode, output in master mode.

SPI_D2

InOut

Data 2. Transfers serial data in quad mode. Open-drain when ODM mode is enabled.

SPI_D3

InOut

Data 3. Transfers serial data in quad mode. Open-drain when ODM mode is enabled.

SPI_MISO

InOut

Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual and

quad modes. Open-drain when ODM mode is enabled.

SPI_MOSI

InOut

Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual and

quad modes. Open-drain when ODM mode is enabled.

SPI_RDY

InOut

Ready. Optional flow signal. Output in slave mode, input in master mode.

Table 9. ADSP-SC595/SC596/SC598 Detailed Signal Descriptions (Continued)

Signal Name

Direction Description

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