ADSP-SC596 datasheet(83/134 Pages) AD

83 / 134 page

Rev. PrD

Page 83 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Asynchronous Sample Rate Converter (ASRC)—Serial Output Port

For the serial output port, the frame sync is an input and it must meet setup and hold times with regard to SCLK0 on the output port. The

serial data output has a hold time and delay specification with regard to the serial clock. In TDM mode, the ASRC drives at the rising edge

and samples at the falling edge of the serial clock. In all other modes, the serial clock rising edge is the sampling edge, and the falling edge

is the driving edge.

Figure 19. ASRC Serial Output Port Timing

Table 49. ASRC, Serial Output Port

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSRCSFS

1 The serial clock, data, and frame sync signals can originate from any of the DAI pins. The serial clock and frame sync signals can also originate via PCG or SPORTs. The input

of the PCG can be either CLKIN, SCLK0, or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge

tSRCHFS

Frame Sync Hold After Serial Clock Rising Edge

5.5

tSRCCLKW

Clock Width

tSCLK0 – 1

tSRCCLK

Clock Period

2 × tSCLK0

Switching Characteristics

tSRCTDD

Transmit Data Delay After Serial Clock Falling Edge

13.3

tSRCTDH

Transmit Data Hold After Serial Clock Falling Edge

DAI0_PIN20–1

(SCLK0)

SAMPLE EDGE

DAI0_PIN20–1

(FS)

DAI0_PIN20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS

tSRCHFS

tSRCTDD

tSRCTDH

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