ADSP-SC596 datasheet(93/134 Pages) AD

93 / 134 page

Rev. PrD

Page 93 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

OSPI Port—Master Timing

OSPI0

Table 56 and Figure 27 describe the OSPI port master operations. Slave mode is not supported for OSPI.

When internally generated, the programmed SPI clock (fOSPICLKPROG) frequency in megahertz is set by the following equations:

where PRG_MBD is the master mode baud rate divisor.

Note that

• In dual-mode data transmit, the OSPI0_MISO signal is also an output.

• In quad-mode data transmit, the OSPI0_MISO, OSPI0_D2, and OSPI0_D3 signals are also outputs.

• In octal-mode data transmit, the OSPI0_MISO, OSPI0_D2, OSPI0_D3, OSPI0_D4, OSPI0_D5, OSPI0_D6, and OSPI0_D7 signals

are also outputs.

• In dual-mode data receive, the OSPI0_MOSI signal is also an input.

• In quad-mode data receive, the OSPI0_MOSI, OSPI0_D2, and OSPI0_D3 signals are also inputs.

• In octal-mode data receive, the OSPI0_MISO, OSPI0_D2, OSPI0_D3, OSPI0_D4, OSPI0_D5, OSPI0_D6, and OSPI0_D7 signals are

also outputs.

• CPHA is a configuration bit in the OSPI0_CTL register.

Table 56. OSPI0 Port—Master Timing1

1 All specifications apply to OSPI0 only.

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSSPIDM

Data Input Valid to OSPI0_CLK Sampling Edge

(Data Input Setup) 2

2 tSSPIDM and tHSPIDM specifications are characterized for OSPI0_RDC settings of 2 for DDR mode and 3 for SDR mode.

tSYSCLK + TBD

tHSPIDM OSPI0_CLK Sampling Edge to Data Input Invalid

(Data Input Hold)2

TBD

Switching Characteristics

tSDSCIM OSPI0_SEL Low to First OSPI0_CLK Edge

3 PRG_CSSOT = chip select start of transfer (defined in OSPI0_DLY[7:0]).

TBD × tOSPICLKPROG + PRG_CSSOT ×

tSYSCLK – TBD

tSPICHM OSPI0_CLK High Period

4 See Table 22 for details on the minimum period that can be programmed for tSPICLKPROG.

TBD × tOSPICLKPROG – TBD

tSPICLM

OSPI0_CLK Low Period4

TBD × tOSPICLKPROG – TBD

tSPICLK

OSPI0_CLK Period4

tOSPICLKPROG – TBD

tHDSM

Last OSPI0_CLK Edge to OSPI0_SEL High for Mode = 05

5 PRG_CSEOT = chip select end of transfer (defined in OSPI0_DLY[15:8]).

PRG_CSEOT × tSYSCLK – TBD

Last OSPI0_CLK Edge to OSPI0_SEL High for Mode = 35, 6

6 Mode = clock phase and clock polarity bits (defined inOSPI0_CTL[2:1]).

PRG_CSEOT × tSYSCLK + TBD ×

tOSPICLKPROG – TBD

tDDSPIDM OSPI0_CLK Edge to Data Out Valid to Driving Edge

(Data Out Delay)7

7 PRG_WRHLD = transmit delay to improve output hold (defined in OSPI0_RDC[19:16]).

(PRG_WRHLD + TBD) × tSYSCLK +

TBD

tHDSPIDM OSPI0_CLK Edge to Data Out Invalid to Driving Edge

(Data Out Hold)7

PRG_WRHLD × tSYSCLK – TBD

fSYSCLK

fCDU_CLKO10

fOSPICLKPROG

fSYSCLK

PRG_MBD

--------------------

tOSPICLKPROG

fOSPICLKPROG

----------------------

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