ADSP-SC596 datasheet(98/134 Pages) AD

98 / 134 page

Rev. PrD

Page 98 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Universal Serial Bus (USB) Timing

Table 63 provides the timing for the input and output direction for USB SDR mode.

Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing

The UART ports receive and transmit operations are described in the ADSP-SC595/SC596/SC598 SHARC+ Processor Hardware

Reference.

Controller Area Network FD (CANFD) Interface

The CANFD interface timing is described in the ADSP-SC595/SC596/SC598 SHARC+ Processor Hardware Reference.

Table 63. USB Timing SDR Mode

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSD

Input Data Setup Time

tHD

Input Data Hold Time

1.5

tSC

Input Control Setup Time

tHC

Input Control Hold Time

1.5

Switching Characteristics

tDD

Output Data Delay

tDC

Output Control Delay

Figure 33. USB Timing

tHC

USBC0_CLK

tSC

tSD

tHD

tDC

tDD

CONTROL IN

(USBC0_NXT, USBC0_DIR)

DATA IN

(USBC0_DATA0 TO USBC0_DATA7)

CONTROL OUT

(USBC0_STOP)

tDC

DATA OUT

(USBC0_DATA0 TO USBC0_DATA7)

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