MB90F482 datasheet(102/113 Pages) FUJITSU

102 / 113 page

MB90480/485 Series

102

(16) Chip Select Output Timing

(VCC

= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

* : tCP : See “ (1) Clock Timing Standards”.

Note : Due to the configuration of the internal bus, changes in the chip select output signal are clock synchronous

and therefore may causes bus conflict conditions. AC cannot be warranted between the ALE output signal

and the chip select output signal.

Parameter

Sym-

bol

Pin name

Condi-

tions

Value

Unit

Remarks

Min

Max

Chip select output valid time

→RD↓

tSVRL

CS0 to CS3,



tCP*

/ 2 − 7



Chip select output valid

time

→WR↓

tSVWL

CS0 to CS3,

WRH, WRL



tCP*

/ 2 − 7



↑→chip select output valid

time

tRHSV

RD,

CS0 to CS3



tCP*

/ 2 − 17



↑→chip select output

valid time

tWHSV

WRH, WRL,

CS0 to CS3



tCP*

/ 2 − 17



tSVRL

tSVWL

tWHSV

tRHSV

0.8 V

2.4 V

0.8 V

A23 to A16

CS0 to CS3

D15 to D00

WRH, WRL

D15 to D00

Read data

Write data

Unde-

fined

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