CC1010-RTY1 datasheet(55/152 Pages) TI

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CC1010

SWRS047

Page 55 of 152

CKCON (0x8E) - Timer Clock rate Control Register

Bit

Name

R/W

Reset value

Description

Reserved, read as 0

T1M

R/W

Timer 1 clock select.

T1M has no effect in counter mode.

0 : Timer 1 uses the

µC clock divided by 12 (for

compatibility with the 80C32)

1 : Timer 1 uses the

µC clock divided by 4

T0M

R/W

Timer 0 clock select.

T0M has no effect in counter mode.

0 : Timer 0 uses the

µC clock divided by 12 (for

compatibility with the 80C32)

1 : Timer 0 uses the

µC clock divided by 4

2:0

MD(2:0)

R/W

001

MD(2:0) controls the memory stretch cycles when

accessing the external RAM. The reset value is 001, but

for faster access to external RAM,

MD(2:0) should

always be written 000.

16.2.2

Mode 0

Mode 0 operation is illustrated for timer or

counter 0 and 1 in Figure 8. The timer /

counter uses bit 0 to 4 of TL0 / TL1 and all

8 bits of TH0 / TH1 as a 13 bit counter.

TCON.TR0 / TCON.TR1 must be set to

enable the Timer / Counter.

The

bit in TMOD selects the Timer or

Counter clock source as described.

Transitions are counted from the selected

source, as long as TMOD.GATE0 /

TMOD.GATE1 is 0, or TMOD.GATE0 /

TMOD.GATE1 is 1 and the corresponding

interrupt

( INT0 / INT1 )

deasserted.

When the 13-bit count increments from

0x1FFF (all ones), the counter rolls over to

all zeros. The overflow flag TCON.TF0 /

TCON.TF1 is then set.

The 3 most significant bits in TL0 / TL1

are undetermined in Mode 0, and should

be masked by software for evaluation.

In Mode 0, the timer timeout period is

determined by:

(

)(

)

xosc

TLx

THx

TxM

CKCON

8192

−

⋅

−

where THx:TLx is the contents of the

THx:TLx registers if this is reloaded in the

interrupt handler, or 0 if no reload is done.

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