CC1010-RTY1 datasheet(56/152 Pages) TI

56 / 152 page

CC1010

SWRS047

Page 56 of 152

System Clk

Divide by 12

Divide by 4

T0 / T1

T0M / T1M

C/T0 / C/T1

TR0 / TR1

GATE0 / GATE1

INT0 / INT1

TL0 / TL1

TH0 / TH1

Mode 0

Mode 1

TF0 / TF1

Timer 0 / Timer 1

interrupt request

Clock

Figure 8. Mode 0 and Mode 1 operation for Timer / Counter 0 or 1

16.2.3

Mode 1

Mode 1 operation is illustrated for Timer /

Counter 0 and 1 in Figure 8. The counter

is configured as a 16-bit counter, as

compared to the 13 bits in Mode 0, and all

bits in TL0 or TL1 are thus used. The

counter

overflows

when

the

count

increments from 0xFFFF.

Otherwise, Mode 1 operation is the same

as Mode 0.

In Mode 1, the timer timeout period is

determined

by:

()(

)

xosc

TLx

THx

TxM

CKCON

65536

−

⋅

−

where THx:TLx is the contents of the

THx:TLx registers if this is reloaded in the

interrupt handler, or 0 if no reload is done.

16.2.4

Mode 2

Mode 2 operation is illustrated for Timer /

Counter 0 and 1 in Figure 9. Mode 2

operates

8-bit

counter

with

automatic reload of the start value.

The Timer / Counter is controlled as for

Mode 0 and Mode 1, but when TL0 / TL1

overflows, TH0 / TH1 is loaded into TL0 /

TL1.

In Mode 2, the timer timeout period is

determined by:

(

)(

)

xosc

THx

TxM

CKCON

−

⋅

−

256

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