TDA4VEN...Q1 datasheet(115/236 Pages) TI

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6.9.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source

Figure 6-20 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8V

LVCMOS square-wave digital clock source.

Note

1. A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up.

This is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that can

enter an unknown state when DC is applied to the input. Therefore, application software must

power down MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.

2. The LVCMOS clock signal sourcing the MCU_OSC0_XI input must have monotonic transitions.

The clock source should be connected to MCU_OSC0_XI with a point-to-point connection,

via a series termination resistor placed near the clock source. The series termination resistor

value should match the clock source output impedance to the transmission line impedance. For

example, the series termination resistor value needs to be 20 ohms if the clock source has an

output impedance of 30 ohms and the PCB signal trace has a characteristic impedance of 50

ohms. This allows the reflection that returns from the far end of the un-terminated transmission

line to be completely absorbed such that is does not introduce any non-monotonic events on the

signal.

3. The PCB trace length connecting the LVCMOS clock source to MCU_OSC0_XI should be

minimized. This reduces capacitive loading and decreases probability of external noise sources

coupling into the clock signal. Reduced capacitive loading improves rise/fall times of the clock

signal which reduces the probability of jitter being introduced in the system.

Device

MCU_OSC0_XO

MCU_OSC0_XI

AM65x_MCU_OSC_EXT_CLK_03

PCB Ground

Figure 6-20. 1.8V LVCMOS-Compatible Clock Input

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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