TDA4VEN...Q1 datasheet(120/236 Pages) TI

120 / 236 page

6.9.4.2 Output Clocks

The device provides several system clock outputs. Summary of these output clocks are as follows:

• MCU_SYSCLKOUT0

– MCU_PLL0_HSDIV0_CLKOUT (MCU_SYSCLKOUT0) divided by 4 and sent out of the device as

MCU_SYSCLKOUT0. This clock output is provided for test and debug purposes only.

• MCU_OBSCLK0

– Observation clock output for test and debug purposes only.

• WKUP_CLKOUT0

– WKUP domain CLKOUT0 output.

• SYSCLKOUT0

– MAIN_PLL0_HSDIV0_CLKOUT (SYSCLKOUT0) divided by 4 and then sent out of the device as

SYSCLKOUT0. This clock output is provided for test and debug purposes only.

• CLKOUT0

– CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL2_HSDIV1_CLKOUT) divided-by-5 or divided-

by-10. This clock output was provided as an optional source to the external PHY. When configured

to operate as the RMII Clock source (50MHz) the signal must also be routed back to the respective

RMII[x]_REF_CLK pin for proper device operation.

• OBSCLK[1:0]

– Observation clock outputs for test and debug purposes only.

• AUDIO_EXT_REFCLK[1:0]

– Option of sourcing one of six McASP high-frequency audio reference clocks,

MAIN_PLL1_HSDIV6_CLKOUT, or MAIN_PLL2_HSDIV8_CLKOUT when configured to operate as an

output.

6.9.4.3 PLLs

Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from

off-chip power-sources.

There is one PLL in the MCU domain:

• MCU PLL

There are nine PLLs in the MAIN domain:

• MAIN PLL

• PER0 PLL

• PER1 PLL

• GPU PLL

• ARM0 PLL

• DDR PLL

• SMS PLL

• DSS PLL0

• DSS PLL1

• DSS PLL2

The system designer should consider the reference clock source start-up time and the PLL lock requirements

before configuring and using any of the PLL outputs as clock sources. The device reference clock input

requirements are defined in Section 6.9.4.1, Input Clocks / Oscillators. PLL configuration details are described in

the device TRM.

For more information on PLLs, see the PLL subsection in the Clocking subsection of the Device Configuration

section in the device TRM.

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

120

Submit Document Feedback

Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1

TDA4VEN...Q1 Scheda tecnica(PDF) 120 Page - Texas Instruments

TDA4VEN...Q1 Scheda tecnica(HTML) 120 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL