HYB18T512400B datasheet(38/68 Pages) QIMONDA

38 / 68 page

Internet Data Sheet

Rev. 1.1, 2007-05

03292006-YBYM-WG0Z

HYB18T512[40/80/16]0B[C/F]

512-Mbit Double-Data-Rate-Two SDRAM

TABLE 41

Definition for IDD

Self-Refresh Current

CKE

≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data

bus inputs are floating.

DD6

1)2)3)4)5)

Operating Bank Interleave Read Current

1. All banks interleaving reads,

OUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD),

RC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs

are stable during deselects; Data bus is switching.

2. Timing pattern:

DD7

1)2)3)4)5)6)

DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)

DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)

DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)

DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks)

DDR2-800-666: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D(23 clocks)

DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V

DD specifications are tested after the device is properly initialized.

DD parameter are specified with ODT disabled.

4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.

5) Definitions for

DD: see Table 41

6) A = Activate, RA = Read with Auto-Precharge, D=DESELECT

Parameter

Description

LOW

defined as

IN ≤ VIL(ac).MAX

HIGH

defined as

IN ≥ VIH(ac).MIN

STABLE

defined as inputs are stable at a HIGH or LOW level

FLOATING

defined as inputs are

REF = VDDQ / 2

SWITCHING

defined as: Inputs are changing between high and low every other clock (once per two clocks) for address

and control signals, and inputs changing between high and low every other clock (once per clock) for DQ

signals not including mask or strobes

Parameter

Symbol Note

HYB18T512400B Scheda tecnica(PDF) 38 Page - Qimonda AG

HYB18T512400B Scheda tecnica(HTML) 38 Page - Qimonda AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Scheda tecnica Scarica

Link URL