HYB18T512400B datasheet(32/68 Pages) QIMONDA

32 / 68 page

Internet Data Sheet

Rev. 1.1, 2007-05

03292006-YBYM-WG0Z

HYB18T512[40/80/16]0B[C/F]

512-Mbit Double-Data-Rate-Two SDRAM

TABLE 33

OCD Default Characteristics

Symbol

Description

Min.

Nominal

Max.

Unit

Note

—

Output Impedance

—

Ω

1)2)

DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V

2) Impedance measurement condition for output source dc current:

DDQ = 1.7 V, VOUT = 1420 mV; (VOUT–VDDQ) / IOH must be less than

23.4 Ohms for values of

OUT between VDDQ and VDDQ – 280 mV. Impedance measurement condition for output sink dc current: VDDQ =

1.7 V;

OUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV.

—

Pull-up / Pull down mismatch

—

Ω

1)2)3)

3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.

—

Output Impedance step size

for OCD calibration

0—

1.5

Ω

4) This represents the step size when the OCD is near 18 Ohms at nominal conditions across all process parameters and represents only

the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18

± 0.75 Ohms under nominal

conditions.

OUT

Output Slew Rate

1.5

—

5.0

V / ns

1)5)6)7)

5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.

This is verified by design and characterization but not subject to production test.

6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in

DQSQ and tQHS

specification.

7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.

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