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HYB18T512400B Scheda tecnica(PDF) 13 Page - Qimonda AG |
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HYB18T512400B Scheda tecnica(HTML) 13 Page - Qimonda AG |
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13 / 68 page ![]() Internet Data Sheet Rev. 1.1, 2007-05 13 03292006-YBYM-WG0Z HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM FIGURE 1 Chip Configuration for ×4 components, PG-TFBGA-60 (top view) Notes 1. V DDL and VSSDL are power and ground for the DLL. VDDL is connected to V DD on the device. VDD, VDDQ, VSSDL, VSS, and V SSQ are isolated on the device. 2. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit |
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