HYB18T512400B datasheet(49/68 Pages) QIMONDA

49 / 68 page

Internet Data Sheet

Rev. 1.1, 2007-05

03292006-YBYM-WG0Z

HYB18T512[40/80/16]0B[C/F]

512-Mbit Double-Data-Rate-Two SDRAM

32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual

JIT.PER of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has

JIT.PER.MIN = – 72 ps

and

JIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX

JIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).

33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual

JIT.DUTY of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has

JIT.DUTY.MIN = – 72 ps

and

JIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX

JIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).

34) For these parameters, the DDR2 SDRAM device is characterized and verified to support

nPARAM = RU{tPARAM / tCK.AVG}, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support

nRP = RU{tRP / tCK.AVG}, which is in

clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which

RP = 15 ns, the device will support

nRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at

Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.

35)

WTR is at lease two clocks (2 x tCK) independent of operation frequency.

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