HYB18T512400B datasheet(25/68 Pages) QIMONDA

25 / 68 page

Internet Data Sheet

Rev. 1.1, 2007-05

03292006-YBYM-WG0Z

HYB18T512[40/80/16]0B[C/F]

512-Mbit Double-Data-Rate-Two SDRAM

Truth Tables

The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two

SDRAM.

TABLE 19

Command Truth Table

Function

CKE

CS RAS

CAS WE BA0

BA1

A[12:11]

A10 A[9:0]

Note1)2)3)

1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

2) “X” means “H or L (but a defined logic level)”.

3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

Cycle

Current

Cycle

(Extended) Mode

OP Code

4)5)

4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.

5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.

Auto-Refresh

Self-Refresh Entry

4)6)

6) VREF must be maintained during Self Refresh operation.

Self-Refresh Exit

4)6)7)

7) Self Refresh Exit is asynchronous.

Single Bank Precharge

4)5)

Precharge all Banks

Bank Activate

Row Address

4)5)

Write

Column

Column 4)5)8)

8) Burst reads or writes at BL = 4 cannot be terminated.

Write with Auto-

Precharge

Column

Column 4)5)8)

Read

Column

Column 4)5)8)

Read with Auto-

Precharge

Column

Column 4)5)8)

No Operation

Device Deselect

Power Down Entry

4)9)

9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh

requirements.

Power Down Exit

4)9)

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