HYB18T512400B datasheet(52/68 Pages) QIMONDA

52 / 68 page

Internet Data Sheet

Rev. 1.1, 2007-05

03292006-YBYM-WG0Z

HYB18T512[40/80/16]0B[C/F]

512-Mbit Double-Data-Rate-Two SDRAM

Average periodic refresh Interval

REFI

—3.9

µs

15)17)

Auto-Refresh to Active/Auto-Refresh

command period

RFC

105

—

16)

Precharge-All (4 banks) command period

—ns

Read preamble

RPRE

0.9

1.1

13)

Read postamble

RPST

0.40

0.60

13)

Active bank A to Active bank B command

period

RRD

7.5

—

13)17)

Active bank A to Active bank B command

period

RRD

—

15)21)

Internal Read to Precharge command delay

RTP

7.5

—

Write preamble

WPRE

0.25

—

Write postamble

WPST

0.40

0.60

18)

Write recovery time for write without Auto-

Precharge

—

Internal Write to Read command delay

WTR

7.5

—

19)

Exit power down to any valid command

(other than NOP or Deselect)

XARD

2—

20)

Exit active power-down mode to Read

command (slow exit, lower power)

XARDS

6 – AL

—

20)

Exit precharge power-down to any valid

command (other than NOP or Deselect)

2—

Exit Self-Refresh to non-Read command

XSNR

RFC +10

—

Exit Self-Refresh to Read command

XSRD

200

—

Write recovery time for write with Auto-

Precharge

WR/tCK

—

21)

DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V.

2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

5) Inputs are not recognized as valid until

REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.

6) The output timing reference voltage level is

TT.

7) For each of the terms, if not already an integer, round to the next highest integer.

CK refers to the application clock period. WR refers to

the WR parameter stored in the MR.

8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.

9) For timing definition, refer to the Component data sheet.

10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate

mis-match between DQS / DQS and associated DQ in any given cycle.

11) MIN (

CL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can

be greater than the minimum specification limits for

CL and tCH).

12) The

HZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving

(

HZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These

parameters are verified by design and characterization, but not subject to production test.

Parameter

Symbol

DDR2–533

Unit

Note

1)2)3)4)5)6)

Min.

Max.

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