CC2640R2FYFVT.B datasheet(30/74 Pages) TI2

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PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TA = 25°C, VDDS = 3.8 V

GPIO pullup current

Input mode, pullup enabled, Vpad = 0 V

277

µA

GPIO pulldown current

Input mode, pulldown enabled, Vpad = VDDS

113

µA

GPIO high/low input transition,

no hysteresis

IH = 0, transition between reading 0 and reading 1

1.67

GPIO low-to-high input transition,

with hysteresis

IH = 1, transition voltage for input read as 0 → 1

1.94

GPIO high-to-low input transition,

with hysteresis

IH = 1, transition voltage for input read as 1 → 0

1.54

GPIO input hysteresis

IH = 1, difference between 0 → 1 and 1 → 0 points

0.4

TA = 25°C

VIH

Lowest GPIO input voltage reliably interpreted as a

«High»

0.8 VDDS(1)

VIL

Highest GPIO input voltage reliably interpreted as a

«Low»

0.2

VDDS(1)

(1)

Each GPIO is referenced to a specific VDDS pin. See the technical reference manual listed in Section 11.3 for more details.

8.26 Thermal Resistance Characteristics

NAME

DESCRIPTION

RSM (°C/W)(1) (2) RHB (°C/W)(1) (2) RGZ (°C/W)(1) (2)

YFV (°C/W)(1) (2)

RθJA

Junction-to-ambient thermal resistance

36.9

32.8

29.6

76.2

RθJC(top) Junction-to-case (top) thermal resistance

30.3

24.0

15.7

0.3

RθJB

Junction-to-board thermal resistance

7.6

6.8

6.2

16.3

PsiJT

Junction-to-top characterization parameter

0.4

0.3

1.8

PsiJB

Junction-to-board characterization parameter

7.4

6.8

6.2

16.3

RθJC(bot) Junction-to-case (bottom) thermal resistance

2.1

1.9

N/A

(1)

°C/W = degrees Celsius per watt.

(2)

These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air).

•

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

•

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

•

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements.

For RSM, RHB, and RGZ, power dissipation of 2 W and an ambient temperature of 70°C is assumed. For YFV, power dissipation of

1.3 W and ambient temperature of 25°C is assumed.

8.27 Timing Requirements

MIN

NOM

MAX

UNIT

Rising supply-voltage slew rate

100

mV/µs

Falling supply-voltage slew rate

mV/µs

Falling supply-voltage slew rate, with low-power flash settings(1)

mV/µs

Positive temperature gradient in standby(2)

No limitation for negative

temperature gradient, or

outside standby mode

°C/s

CONTROL INPUT AC CHARACTERISTICS(3)

RESET_N low duration

µs

(1)

For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see Figure

10-1) must be used to ensure compliance with this slew rate.

(2)

Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see

Section 8.17).

(3)

TA = –40°C to +85°C, VDDS = 1.7 V to 3.8 V, unless otherwise noted.

CC2640R2F

SWRS204C – DECEMBER 2016 – REVISED SEPTEMBER 2020

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