CC2640R2FYFVT.B datasheet(40/74 Pages) TI2

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Table 9-2. Power Modes (continued)

MODE

SOFTWARE CONFIGURABLE POWER MODES

RESET PIN

HELD

ACTIVE

IDLE

STANDBY

SHUTDOWN

Wake up on Reset Pin

Available

Brown Out Detector (BOD)

Active

Duty Cycled

Off

N/A

Power On Reset (POR)

Active

N/A

(1)

Not including RTOS overhead

In active mode, the application CM3 CPU is actively executing code. Active mode provides normal operation of

the processor and all of the peripherals that are currently enabled. The system clock can be any available clock

source (see Table 9-2).

In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked

and no code is executed. Any interrupt event will bring the processor back into active mode.

In standby mode, only the always-on domain (AON) is active. An external wake-up event, RTC event, or sensor-

controller event is required to bring the device back to active mode. MCU peripherals with retention do not need

to be reconfigured when waking up again, and the CPU continues execution from where it went into standby

mode. All GPIOs are latched in standby mode.

In shutdown mode, the device is turned off entirely, including the AON domain and the Sensor Controller. The

I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin

defined as a wake-up from Shutdown pin wakes up the device and functions as a reset trigger. The CPU can

differentiate between a reset in this way, a reset-by-reset pin, or a power-on-reset by reading the reset status

The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller

independently of the main CPU, which means that the main CPU does not have to wake up, for example, to

execute an ADC sample or poll a digital sensor over SPI. The main CPU saves both current and wake-up time

that would otherwise be wasted. The Sensor Controller Studio enables the user to configure the sensor

controller and choose which peripherals are controlled and which conditions wake up the main CPU.

9.9 Clock Systems

The CC2640R2F supports two external and two internal clock sources.

A 24-MHz crystal is required as the frequency reference for the radio. This signal is doubled internally to create a

48-MHz clock.

The 32-kHz crystal is optional. Bluetooth low energy requires a slow-speed clock with better than

±500 ppm accuracy if the device is to enter any sleep mode while maintaining a connection. The internal

32-kHz RC oscillator can in some use cases be compensated to meet the requirements. The low-speed crystal

oscillator is designed for use with a 32-kHz watch-type crystal.

The internal high-speed oscillator (48-MHz) can be used as a clock source for the CPU subsystem.

The internal low-speed oscillator (32.768-kHz) can be used as a reference if the low-power crystal oscillator is

not used.

The 32-kHz clock source can be used as external clocking reference through GPIO.

9.10 General Peripherals and Modules

The I/O controller controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals to be

assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a

programmable pullup and pulldown function and can generate an interrupt on a negative or positive edge

(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs

have high drive capabilities (marked in bold in Section 7).

The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and Texas Instruments

synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz.

CC2640R2F

SWRS204C – DECEMBER 2016 – REVISED SEPTEMBER 2020

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