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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SPSB100 Scheda tecnica(PDF) 174 Page - STMicroelectronics |
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SPSB100 Scheda tecnica(HTML) 174 Page - STMicroelectronics |
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174 / 213 page  Table 244. DSR6 (0x26) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R) 0 (R) 0 (RC1L) 0 (R) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) IRQ_ECHO NRST_ECHO IRQ_SENT NFSO1_ECHO CRC3 CRC2 CRC1 CRC0 Interrupt echo bit NRST echo bit Interrupt sent bit NFSO1_echo bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 245. DSR6 (0x26) LSB description Bit Name Description 7 IRQ_ECHO Indicates current status of IRQ pin. 1: High It is a live bit 6 NRST_ECHO Indicates current status of NRST pin. 1: High It is a live bit 5 IRQ_SENT IRQ sent from IRQ_REQUEST rising 1: IRQ sent 4 NFSO1_ECHO Indicates current status of NFSO1 pin. 1: High It is a live bit 3 CRC 3 2 CRC 2 1 CRC 1 0 CRC 0 Table 246. DSR7 (0x27) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) 0 (RC1L) 0 (RC1L) 0 (R) 0 (RC1L) 0 (R) 0 (R) 0 (R) RES VPOR LDO1_PG_OK LDO2_ENA_STATUS LDO2_PG_OK FCCU_ENA_ECHO WD_ENA_ECHO WD_TIMER_STATE_1 Reserved Vs power on reset bit LDO1 power-good ok bit LDO2 enable status bit LDO2 power-good ok bit FCCU enable echo bit Watchdog enable echo bit Watchdog timer state bit 1 Table 247. DSR7 (0x27) MSB description Bit Name Description 23 RES Reserved 22 VPOR VS power-on reset threshold (VPOR) reached bit is latched until a "Read and clear" command 21 LDO1_PG_OK Indicates power-good LDO1 bit is latched until a “read and clear” command 20 LDO2_ENA_STATUS LDO2 enable status bit. Live bit LDO2 is a tracker and when disabled by SPI or UV or OV, this bit indicates the enable status 1: Enabled 0: Disabled 19 LDO2_PG_OK 1: Power-good reached after the regulator has been turned ON by power-up sequence or through SPI 0: PG not reached SPSB100 SPI registers DS14640 - Rev 2 page 174/213 |
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