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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SPSB100 Scheda tecnica(PDF) 175 Page - STMicroelectronics |
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SPSB100 Scheda tecnica(HTML) 175 Page - STMicroelectronics |
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175 / 213 page  Bit Name Description 18 FCCU_ENA_ECHO echo of FCCU enable signal at FCCU block input 1: Indicates that the FCCU is running Live bit 0: Indicates that FCCU block is disabled 17 WD_ENA_ECHO echo of WD enable signal at WD block input 1: Indicates that the WD is running Live bit 0: Indicates that WD block is disabled It occurs in software debug or in test mode 16 WD_TIMER_STATE_1 Watchdog timer status 00: WD counter in too early window trig 01: WD counter in valid window trig 11: WD counter in too late window trig Table 248. DSR7 (0x27) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (RC1L) WD_TIMER_STATE_0 WDFAIL_CNT_3 WDFAIL_CNT_2 WDFAIL_CNT_1 WDFAIL_CNT_0 TSD_CNT_FAIL_1 TSD_CNT_FAIL_0 POWUP_RETRY_CNT_1 Watchdog timer state bit 0 Watchdog fail count bit 3 Watchdog fail count bit 2 Watchdog fail count bit 1 Watchdog fail count bit 0 Thermal shutdown fail count bit 1 Thermal shutdown fail count bit 0 Power up retry count bit 1 Table 249. DSR7 (0x27) description Bit Name Description 15 WD_TIMER_STATE_0 14 WDFAIL_CNT_3 Indicates number of consecutive watchdog trig fault, from 1 to 15 Bits cannot be cleared, will be cleared with a valid watchdog trig during a long open window, or in DEEP-SLEEP 13 WDFAIL_CNT_2 12 WDFAIL_CNT_1 11 WDFAIL_CNT_0 10 TSD_CNT_FAIL_1 Thermal shut down sequence retry counter 9 TSD_CNT_FAIL_0 8 POWUP_RETRY_CNT_1 Power up sequence retry counter MCU must clear this counter in REC-1 or ACTIVE state Table 250. DSR7 (0x27) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (RC1L) - (R0) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) POWUP_RETRY_CNT_0 RES NVM_PROG_OK NVM_PROG_DONE CRC3 CRC2 CRC1 CRC0 Power up retry count bit 0 Reserved NVM program ok bit NVM program done bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 SPSB100 SPI registers DS14640 - Rev 2 page 175/213 |
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