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DAC39RFS10 Scheda tecnica(PDF) 30 Page - Texas Instruments |
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DAC39RFS10 Scheda tecnica(HTML) 30 Page - Texas Instruments |
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30 / 177 page ![]() 6.9 Switching Characteristics (continued) Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 12 GHz, IFS_SWITCH = 20.5 mA, single tone amplitude = 0 dBFS, Dither and DEM enabled, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t FRCLK _PL FRCLK pulse width low 2 ns t FRDI_SU FRDI setup time 1 ns tFRDI _H FRDI hold time 1 ns t FRCS_SU FRCS setup time 1 ns t FRCS_H FRCS hold time 1 ns tFR_IAG Inter-access gap 1 ns (1) The delay depends on how long it takes the JESD link to start up and the mode dependent device latency. Add the link layer startup time and the mode depedent latency (TDAC_LAT) from the latency calculator spreadsheet. (2) Pulse durations less than this produce undefined behavior. (3) Pulse durations less than this may have no effect on the output. (4) 8b/10b encoding required for < 2 Gbps DDS39RF12, DDS39RFS12 SBASB21 – SEPTEMBER 2024 www.ti.com 30 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DDS39RF12 DDS39RFS12 |
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