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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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DAC39RFS10 Scheda tecnica(PDF) 90 Page - Texas Instruments |
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DAC39RFS10 Scheda tecnica(HTML) 90 Page - Texas Instruments |
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90 / 177 page  JESD204C Mode Figure 7-72. JMODE Register 7 6 5 4 3 2 1 0 RESERVED JMODE R/W-00b R/W-000000b Table 7-44. JMODE Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 00b 5-0 JMODE RW 000000b Specify the JESD204C interface mode. See Table 7-22. Note: This register should only be changed when JESD_EN=0. 7.5.3.12 JESD_M Register (Offset = 0102h) [reset = 01h] JESD_M is shown in Figure 7-73 and described in Table 7-45. Return to the Register Summary Table. JESD204C Number of Streams Figure 7-73. JESD_M Register 7 6 5 4 3 2 1 0 JESD_M R/W-0h R/W-1h Table 7-45. JESD_M Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 JESD_M R/W 1h Specify the number of sample streams to enable (JESD204C M parameter). The supported settings for JESD_M depend on the DUC interpolation (DUC_L) and Mx. LDUC: Supported Settings for JESD_M 1x: 1 or 2 (but never larger than Mx) 2x or 3x: 2 (but never larger than Mx) 4x or 6x: 2 or 4 (but never larger than Mx) 8x or higher:2, 4, 6 or 8 (but never larger than Mx) See Table 7-22 for the Mx value associated with each JMODE. The number of lanes enabled (L) is computed as: L=ceiling(M/Mx*Lx). An I/Q pair counts as two streams. For example, when inputting 4 IQ streams, program JESD_M=8. Note: This register should only be changed when JESD_EN=0 and DP_EN=0. 7.5.3.13 JCTRL Register (Offset = 0103h) [reset = 03h] JCTRL is shown in Figure 7-74 and described in Table 7-46. Return to the Register Summary Table. JESD204C Control. This register should only be changed when JESD_EN = 0. Figure 7-74. JCTRL Register 7 6 5 4 3 2 1 0 DDS39RF12, DDS39RFS12 SBASB21 – SEPTEMBER 2024 www.ti.com 90 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DDS39RF12 DDS39RFS12 |
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