DAC39RFS10 datasheet(98/177 Pages) TI2

98 / 177 page

Figure 7-87. CRC_TH Register (continued)

Table 7-59. CRC_TH Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-2

CRC_ERR_REC

R/W

Specify how many contiguous, error-free multiblocks must be

received to reset the CRC error counter (and un-trigger the CRC

alarm if triggered).

0 : 1 multiblock

1 : 4 multiblocks

2 : 16 multiblocks

3 : 64 multiblocks

1-0

CRC_ERR_TH

R/W

Specify how many multi-blocks must have CRC errors to trigger

the CRC alarm. The receiver counts each error, but if a run of error-

free multi-blocks occurs (as specified by CRC_ERR_REC), the error

counter resets.

0 : 1 multiblock

1 : 2 multiblocks

2 : 4 multiblocks

3 : 8 multiblocks

Note: For each lane, the internal signal, CRC_FAULT, is set if the number of multi-blocks with CRC errors exceeds the threshold set by

CRC_ERR_TH without a run of contiguous, error-free multi-blocks specified by CRC_ERR_REC. CRC_FAULT is cleared when a run of

contiguous, error-free multi-blocks specified by CRC_ERR_REC is detected.

Note: This register should only be changed when JESD_EN=0.

7.5.3.27 LANE_ARSTAT Register (Offset = 012Ch) [reset = NA]

LANE_ARSTAT is shown in Figure 7-88 and described in Table 7-60.

Return to the Register Summary Table.

Lane Arrival Status

Figure 7-88. LANE_ARSTAT Register

RESERVED

LANE_ARR_R

R/W-00h

Table 7-60. LANE_ARSTAT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

LANE_ARR_RDY

This bit is set when lane arrival times are captured and available for

read in LANE_ARR. Lane arrival data is captured when all lanes are

ready and the chip attempts to release the elastic buffer. This bit is

cleared when JESD_EN=0 or JESD_RST=1.

7.5.3.28 LANE_INV Register (Offset = 012Eh) [reset = 0000h]

LANE_INV is shown in Figure 7-89 and described in Table 7-61.

Return to the Register Summary Table.

DDS39RF12, DDS39RFS12

SBASB21 – SEPTEMBER 2024

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