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DAC39RFS10 Scheda tecnica(PDF) 95 Page - Texas Instruments |
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DAC39RFS10 Scheda tecnica(HTML) 95 Page - Texas Instruments |
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95 / 177 page  Table 7-53. RATE Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 RATE R/W 00b Controls the frequency multiplier from the PHY PLL to the serial line rate. See PLL Control. Affects all lanes. RATE: Multiplier 00b: 4 01b: 2 10b: 1 11b: 0.5 Note: This register should only be changed when JESD_EN=0. 7.5.3.21 LB_VRANGE Register (Offset = 010Bh) [reset = 00h] LB_VRANGE is shown in Figure 7-82 and described in Table 7-54. Return to the Register Summary Table. JESD204C PLL VCO Range. Note: This register should only be changed when JESD_EN=0. Figure 7-82. LB_VRANGE Register 7 6 5 4 3 2 1 0 RESERVED VRANGE R/W-0h R/W-0b Table 7-54. LB_VRANGE Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 VRANGE R/W 0b This bit must be set if the PLL/VCO frequency is below 2.17GHz. See PLL Control. 7.5.3.22 JSYNC_N Register (Offset = 0120h) [reset = 01h] JSYNC_N is shown in Figure 7-67 and described in Table 7-39. Return to the Register Summary Table. JESD204C Manual Sync Request Figure 7-83. JSYNC_N Register 7 6 5 4 3 2 1 0 RESERVED JSYNC_N R/W-00h R/W1C Table 7-55. JSYNC_N Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 JSYNC_N R/W 1b Set this bit to 0 to manually assert the SYNC signal. For normal operation, leave this bit set to 1. Note: Behavior of JSYNC_N=0 is undefined when JENC=1. 7.5.3.23 JTEST Register (Offset = 0121h) [reset = 00h] JTEST is shown in Figure 7-84 and described in Table 7-56. www.ti.com DDS39RF12, DDS39RFS12 SBASB21 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: DDS39RF12 DDS39RFS12 |
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