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DAC39RFS10 Scheda tecnica(PDF) 85 Page - Texas Instruments |
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DAC39RFS10 Scheda tecnica(HTML) 85 Page - Texas Instruments |
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85 / 177 page  Table 7-32. SPI Registers (continued) Offset Acronym Register Name Section 0x0727 DEM_ADJ DEM Adjust Go 0x0728 RESERVED 0x0729 DEM_DITH DEM and DITHER Control Go 0x72A-0x072D DAC_OFS DAC_Offset_Adjustment Go 0x72E - 0x7FF RESERVED 7.5.3.1 CONFIG_A Register (Offset = 0h) [reset = 30h] CONFIG_A is shown in Figure 7-61 and described in Table 7-33. Return to the Register Summary Table. Configuration A (default: 0x30) Figure 7-61. CONFIG_A Register 7 6 5 4 3 2 1 0 SOFT_RESET RESERVED ASCEND RESERVED RESERVED R/W-0h R/W-0h R/W-1h R/W-1h R/W-0h Table 7-33. CONFIG_A Register Field Descriptions Bit Field Type Reset Description 7 SOFT_RESET R/W 0h Writing a 1 to this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing and will always read zero. After writing this bit, the part may take up to 5 ns to reset. During this time, do not perform any SPI transactions. 6 RESERVED R/W 0h 5 ASCEND R/W 1h 0 : Address is decremented during streaming reads/writes 1 : Address is incremented during streaming reads/writes (default) 4 RESERVED R 1h Always read 1. 3-0 RESERVED R/W 0h 7.5.3.2 DEVICE_CONFIG Register (Offset = 2h) [reset = 00h] DEVICE_CONFIG is shown in Figure 7-62 and described in Table 7-34. Return to the Register Summary Table. Device Configuration (default: 0x00) Figure 7-62. DEVICE_CONFIG Register 7 6 5 4 3 2 1 0 RESERVED MODE R/W-0h R/W-0h Table 7-34. DEVICE_CONFIG Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h www.ti.com DDS39RF12, DDS39RFS12 SBASB21 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: DDS39RF12 DDS39RFS12 |
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