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DAC39RFS10 Scheda tecnica(PDF) 47 Page - Texas Instruments |
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DAC39RFS10 Scheda tecnica(HTML) 47 Page - Texas Instruments |
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47 / 177 page ![]() CLK+ CLK– DAC Output (Sine Wave) 0 +VFS -VFS TS = 1/FCLK tpd TS /2 Figure 7-7. RF Mode Timing Diagram FOUT/FCLK 0 0.5 1 1.5 2 2.5 3 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 Figure 7-8. RF Mode Output Frequency Response 7.3.1.4 DES Mode Dual edge sampling (DES) mode outputs unique samples on both the rising and falling edge of CLK, doubling the sample rate for the same clock frequency. An extra digital interpolate by 2 stage is included in the device to enable a double sample rate. An non-50% CLK duty cycle results in an image of the signal at FCLK - FOUT. Compared to NRZ mode with the same clock frequency, DES mode provides significant reduction in the image amplitude, reducing filter requirements. DES2XL uses an low pass 2x interpolation filter to increase from the single edge sample rate to dual edge sample rate, and supports output frequencies between 0 - 0.4*FCLK. DES2XH uses a high pass interpolation filter, supporting output frequencies between 0.6 - 1.0*FCLK with the same signal BW as DES2XL. www.ti.com DDS39RF12, DDS39RFS12 SBASB21 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: DDS39RF12 DDS39RFS12 |
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