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LMKDB1104FS85 Scheda tecnica(PDF) 27 Page - Texas Instruments

Il numero della parte LMKDB1104FS85
Spiegazioni elettronici  LMKDB12xx PCIe Gen 1 to Gen 7 Ultra Low Jitter 2 Input Clock MUX
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LMKDB1104FS85 Scheda tecnica(HTML) 27 Page - Texas Instruments

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8.3.4.3 Programmable Output Slew Rate
The LMKDB family offers slew rate control options through SMBus and pin modes. The pin mode option is
global slew rate control for all the outputs. SMBus slew rate control supports programmable output slew rate for
each individual output. The slew rate is heavily dependent on trace characteristics including trace width, copper
thickness, substrate height, dielectric constant, and loss tangent.
LMKDB slew rate control settings are tested with PCIe test load shown in Figure 7-1.
8.3.4.3.1 Slew Rate Control Through SMBus
The LMKDB12xx has 16 different slew rates options that can be assigned to the outputs. 0x0 is the fastest slew
rate setting and 0xF is the slowest slew rate setting. To set the slew rate of each output, follow these steps:
1. There are four different registers, SLEWRATE_OPT#, that can store up to four different slew rates. Select
your desired slew rates by assigning a value from 0x0 (fastest) to 0xF (slowest) to each SLEWRATE_OPT#
register. The default values set to each SLEWRATE_OPT# register can be found in Table 8-4.
a. For example, if you wanted the fastest, second fastest, and the slowest slew rate, assign 0x0, 0x1,
and 0xF to registers SLEWRATE_OPT#. SLEWRATE_OPT1 = 0x0 (fastest), SLEWRATE_OPT2 = 0x1
(second fastest), and SLEWRATE_OPT3 = 0xF (slowest). SLEWRATE_OPT4 does not have to be
assigned, but if you want more than one register set to a slew rate, then SLEWRATE_OPT4 can be
assigned to any of the three previous settings.
2. Set a slew rate option for each output by using the SLEWRATE_SEL_CLKX_LSB and
SLEWRATE_SEL_CLKX_MSB as shown in Table 8-4 or drop-down menus under the Output Slew
Rate Control Section in TICSPro. The default SLEWRATE_OPT# register assignment for all outputs is
SLEWRATE_OPT2, which has a default slew rate of 0x6.
The corresponding ranges for the four default slew rates can be found in Section 6 under CLOCK OUTPUT
CHARACTERISTICS - 100MHz 85Ω PCIe or CLOCK OUTPUT CHARACTERISTICS - 100MHz 100Ω PCIe for
the specification Output slew rate.
Table 8-4. LMKDB Default SLEWRATE_OPT_# Values
Register Field Name
Default Value
Default Slew Rate
SLEWRATE_OPT_1
0x0
Highest
SLEWRATE_OPT_2
0x6
High (default for all outputs)
SLEWRATE_OPT_3
0xA
Low
SLEWRATE_OPT_4
0xF
Lowest
Table 8-5. SLEWRATE_SEL_CLKX_LSB & SLEWRATE_SEL_CLKX_MSB Slew Rate Selection
SLEWRATE_SEL_CLKX_LSB
SLEWRATE_SEL_CLKX_MSB
Slew Rate Option Selection
0
0
SLEWRATE_OPT_4
1
0
SLEWRATE_OPT_3
0
1
SLEWRATE_OPT_2
1
1
SLEWRATE_OPT_1
To program the slew rate to the desired slew rate, the following sequence needs to be followed:
1. [Optional]: if the default assignments shown in Table 8-4 for each slew rate speed is not as desired, one of
the slew rate options value can be changed to another slew rate.
2. [LMKDB1108 and 1104 only]: Program SLEWRATE_CTRL_MODE register to 1 to select SMBus
programming mode for slew rate control. Refer to Section 9 section for LMKDB1108 and LMKDB1104
register bits information.
3. Program SLEWRATE_SEL_CLKX_MSB and SLEWRATE_SEL_CLKX_LSB to assign clock output X to
desired slew rate speed option, as shown in Table 8-5. The default assignments for each option can be
found in Table 8-4.
www.ti.com
LMKDB1202, LMKDB1204, LMKDB1208
SNAS927A – AUGUST 2025 – REVISED APRIL 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: LMKDB1202 LMKDB1204 LMKDB1208



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