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LMKDB1104FS85 Scheda tecnica(PDF) 1 Page - Texas Instruments |
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LMKDB1104FS85 Scheda tecnica(HTML) 1 Page - Texas Instruments |
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1 / 69 page ![]() LMKDB12xx PCIe Gen 1 to Gen 7 Ultra Low Jitter 2 Input Clock MUX 1 Features • LP-HCSL clock MUX that support: – PCIe Gen 1 to Gen 7 – CC (Common Clock) and IR (Independent Reference) PCIe architectures – Input clock with or without SSC • DB2000QL compliant: – All devices meet DB2000QL specifications • Extremely low additive jitter: – 31fs maximum 12kHz to 20MHz RMS additive jitter at 156.25MHz – 13fs maximum additive jitter for PCIe Gen 4 – 5fs maximum additive jitter for PCIe Gen 5 – 3fs maximum additive jitter for PCIe Gen 6 – 2.1fs maximum additive jitter for PCIe Gen 7 • Fail-safe input • Flexible power-up sequence • Automatic output disable • Individual output enable • SBI (Side Band Interface) for high-speed output enable or disable • LOS (Loss of Signal) input detection • 85Ω or 100Ω output impedance • 1.8V / 3.3V ± 10% power supply • –40°C to 105°C ambient temperature 2 Applications • High Performance Computing • Server Motherboard • NIC/SmartNIC • Hardware Accelerator 3 Description The LMKDB devices are a family of extremely-low- jitter LP-HCSL clock muxes that support PCIe Gen 1 to Gen 7 and are DB2000QL compliant. The devices provide flexible power-up sequence, fail-safe inputs, individual output enable and disable pins, loss of input signal (LOS) detection and automatic output disable features, as well as excellent power supply noise rejection performance. Both 1.8V and 3.3V power supply voltages are supported. Package Information PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LMKDB1208 RSL (VQFN, 48) 6mm × 6mm LMKDB1204 REX (VQFN, 28) 4mm × 4mm LMKDB1202 REY (VQFN, 20) 3mm × 3mm (1) For all available packages, see Section 13. (2) The package size (length × width) is a nominal value and includes pins, where applicable. PCIe Clock Source #1 LMKDB family PCIe Clock MUX SMBus Control OE# Control PCIe PHY PCIe PHY PCIe PHY PCIe PHY LP-HCSL PCIe PHY PCIe PHY PCIe Device Side-Band Interface Control Interface PCIe Clock Source #2 Typical Application LMKDB1202, LMKDB1204, LMKDB1208 SNAS927A – AUGUST 2025 – REVISED APRIL 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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