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LMKDB1104FS85 Scheda tecnica(PDF) 45 Page - Texas Instruments

Il numero della parte LMKDB1104FS85
Spiegazioni elettronici  LMKDB12xx PCIe Gen 1 to Gen 7 Ultra Low Jitter 2 Input Clock MUX
PDF  69 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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LMKDB1104FS85 Scheda tecnica(HTML) 45 Page - Texas Instruments

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9.2.14 R15 Register (Offset = Fh) [Reset = 19h]
R15 is shown in Table 9-39.
Return to the Summary Table.
Table 9-39. R15 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CLK_OEB_EN_7
R/W
0h
Enable OE7b pin to control CLK7
0h = output stop by OEb is disabled
1h = output stop by OEb is enabled
6:5
RESERVED
R
0h
Reserved bits
4
CLK_OEB_EN_6
R/W
1h
Enable OE6b pin to control CLK6
0h = output stop by OEb is disabled
1h = output stop by OEb is enabled
3
CLK_OEB_EN_5
R/W
1h
Enable OE5b pin to control CLK5
0h = output stop by OEb is disabled
1h = output stop by OEb is enabled
2:1
RESERVED
R
0h
Reserved bits
0
CLK_OEB_EN_4
R/W
1h
Enable OE4b pin to control CLK4
0h = output stop by OEb is disabled
1h = output stop by OEb is enabled
9.2.15 R17 Register (Offset = 11h) [Reset = 66h]
R17 is shown in Table 9-40.
Return to the Summary Table.
Table 9-40. R17 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
AMP_1
R/W
6h
BANK1 Differential output Control = 0.6V to approximately 1V
25mV/step Default = 0.75V
0h = 600mV
1h = 625mV
2h = 650mV
3h = 675mV
4h = 700mV
5h = 725mV
6h = 750mV
7h = 775mV
8h = 800mV
9h = 825mV
Ah = 850mV
Bh = 875mV
Ch = 900mV
Dh = 925mV
Eh = 950mV
Fh = 975mV
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LMKDB1202, LMKDB1204, LMKDB1208
SNAS927A – AUGUST 2025 – REVISED APRIL 2026
Copyright © 2026 Texas Instruments Incorporated
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Product Folder Links: LMKDB1202 LMKDB1204 LMKDB1208



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